Method and apparatus for redundancy word line replacement in a repairable semiconductor memory device

A semiconductor memory device comprising:

• memory cells arranged in rows and columns, said memory cells including normal memory cells and redundant memory cells for replacing defective ones of said normal memory cells;
• bit line pairs connected to said memory cells, each bit line pair consisting of first and second bit lines which are respectively connected to memory cells for storing true data and memory cells for storing complementary data in corresponding ones of said columns;
• word lines, said word lines including normal word lines each respectively connected to said normal memory cells in a corresponding one of said rows and redundant word lines each respectively connected to said redundant memory cells in a corresponding one of said rows, said normal word lines including a first normal word line for selecting a first normal memory cell for storing true data connected to the first bit line of one of said bit line pairs and a second normal word line for selecting a second normal memory cell for storing complementary data connected to the second bit line of said one of said bit line pairs, and said redundant word lines including a first redundant word line for selecting a first redundant memory cell for storing true data connected to the first bit line of said one of said bit line pairs and a second redundant word line for selecting a second redundant memory cell for storing complementary data connected to the second bit line of said one of said bit line pairs,
• said first normal word lines being replaced by the same number of said first redundant word lines, wherein ordering said first normal word lines is independent of ordering said first redundant word lines, and
• said second normal word lines being replaced by the same number of said second redundant word lines, wherein ordering said second normal word lines is independent of ordering said second redundant word lines;
• address ordering means for reordering an addressing sequence of said true and said complementary word lines;
• and
• decoding means responsive to a word line enable signal, to at least one redundant word line enable signal, and to at least one address input.

A semiconductor memory device comprising:

• memory cells arranged in rows and columns, said memory cells including normal memory cells and redundant memory cells for replacing defective ones of said normal memory cells;
• bit lines pairs connected to said memory cells, each bit line pair consisting of first and second bit lines which are respectively connected to memory cells for storing true data and memory cells for storing complementary data in corresponding ones of said columns;
• word lines, said word lines including normal word lines each respectively connected to said normal memory cells in a corresponding one of said rows and redundant word lines each respectively connected to said redundant memory cells in a corresponding one of said rows, said normal word lines including a first normal word line for selecting a first normal memory cell for storing true data connected to the first bit line of one of said bit line pairs and a second normal word line for selecting a second normal memory cell for storing complementary data connected to the second bit line of said one of said bit line pairs, and said redundant word lines including a first redundant word line for selecting a first redundant memory cell for storing true data connected to the first bit line of said one of said bit line pairs and a second redundant word line for selecting a second redundant memory cell for storing complementary data connected to the second bit line of said one of said bit line pairs,
• said first normal word lines being replaced by the same number of said first redundant word lines, wherein ordering said first normal word lines is independent of ordering said first redundant word lines, and
• said second normal word lines being replaced by the same number of said second redundant word lines, wherein ordering said second normal word lines is independent of ordering said second redundant word lines;
• and
• address ordering means for reordering an addressing sequence of said true and said second redundant word lines;
• and
• decoding means for maintaining consisting of at least one bit map, wherein said decoding means is responsive to a word line enable signal, to at least one redundant word line enable signal, and to at least one address input.

A method for repairing a semiconductor memory device, the memory device having memory cells connected to bit lines arranged in rows and columns, the memory cells connected to bit lines and including normal memory cells and redundant memory cells, wherein the normal memory cells are connected to first normal word lines and to second normal word lines and the redundant memory cells are connected to first redundant word lines and to second redundant word lines, said method comprising the steps of:

• replacing said first normal word lines by the same number of said first redundant word lines, ensuring that ordering said first normal word lines is independent of ordering said first redundant word lines, and
• replacing said second normal word lines by the same number of said second redundant word lines, ensuring that ordering said second normal word lines is independent of ordering said second redundant word lines;
• and
• maintaining consistency of at least one bit map when ordering said first redundant word lines and said second redundant word lines by way of a selector circuit, the selector circuit being responsive to a word line enable signal, to at least one redundant word line enable signal, and to at least one address input.