Bit switch circuit and bit line selection method
AssigneeInternational Business Machines Corporation
InventorsGus Wai-Yen Yeung, Robert Anthony Ross, Jr., George McNeil Lattimore
Life of this patent
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Abstract
A bit switch circuit (10) includes an amplifier stage (11) and a plurality of input stages (23,33,43,53). Each input stage (23,33,43,53) is connected to receive as inputs the signals applied to a bit line pair associated with a memory array. Each input stage (23,33,43,53) is also associated with a common node (24,34,44,54), and a select transistor (T4, T5, T6, T7). Each select transistor (T4, T5, T6, T7) responds to a select input signal to couple the respective common node (24,34,44,54) to ground. This allows the sense amplifier (11) to respond to the data signals on the bit line pair (20,21,30,31,40,41,50,51) associated with the respective input stage (23,33,43,53).
Claims17
A bit switch circuit for selecting one of a plurality of bit line pairs in a read operation from a digital memory array, the bit switch circuit comprising;
- (a) an amplifier stage having a first output node and a second output node;
- (b) a plurality of input stages, each input stage having a different common node associated therewith, each input stage also being connected to the bit lines of a different bit line pair and connecting the respective common node to the first output node and the second output node;
- and
- (c) a plurality of select transistors, each select transistor being associated with a different input stage and operating to couple the common node of the respective input stage to ground in response to a select signal at the respective select transistor.
A bit switch circuit for selecting one of a plurality of bit line pairs in a read operation from a digital memory array, the circuit comprising:
- (a) a first output node and a second output node;
- (b) a plurality of input stages, each respective input stage associated with a different bit line pair of the plurality of bit line pairs, and each input stage having a first input transistor, a second input transistor, and a common node, the first input transistor having a drain-source conduction path connecting the first output node and the respective common node and having a gate connected to a first bit line of the respective bit line pair, the second input transistor having a drain-source conduction path connecting the second output node and the respective common node and having a gate connected to a second bit line of the respective bit line pair;
- (c) a plurality of select transistors, each select transistor associated with a different input stage and having a drain-source conduction path connecting the respective common node to ground, each select transistor also having a gate connected to receive a select input signal which is unique to the particular select transistor;
- (d) a first amplifier transistor having a source-drain conduction path connecting the first output node to a supply voltage and having a gate connected to the second output node;
- and
- (e) a second amplifier transistor having a source-drain conduction path connecting the second output node to the supply voltage and having a gate connected to the first output node.
A method of selecting from a plurality of bit line pairs during a read operation from a digital memory array, the method comprising the steps of:
- (a) applying the signals from each bit line pair to a different alternate input stage of a sense amplifier, each alternate input stage having a different select transistor associated therewith;
- and
- (b) applying a select input signal to the select transistor associated with a desired one of the alternate input stages.
Dependencies are inferred from the claim text.