Method and apparatus for bit line recovery in dynamic random access memory

#1. Technical Field of the Invention

#The present invention relates to a device and method for recovering data accessed from random access memory cells, and particularly to a device and method for recovering bit line data from a dynamic random access memory (DRAM) cell.

#2. Background of the Invention

#A more complete understanding of the present invention may be had by reference to the following detailed description when taken in conjunction with the accompanying drawings wherein:

#FIG. 1 is a diagram of DRAM bit line recovery circuitry according to a first preferred embodiment of the present invention;

#FIG. 2 is a diagram of DRAM bit line recovery circuitry according to a second preferred embodiment of the present invention; and

#Referring to FIG. 1, there is shown a bit line recovery circuit 1 for a random access memory device, such as a DRAM. The recovery circuit of the present invention is described hereinbelow in conjunction with a single bit line pair for exemplary purposes only. It is understood that the bit line recovery device of the present invention is preferably associated with each bit line pair in a memory device.

#The present invention can be applied to any appropriate memory structure wherein each column comprises a plurality of memory cells connected to a single bit line, and is not restricted to any specific structure of memory cell. The present invention is applicable for stand-alone memory chips but is especially suited memory embedded within an integrated circuit, such as a microprocessor chip or an application specific integrated circuit (ASIC) wherein typically more metal layers may better accommodate the efficient routing between transistor elements.

#A pair of bit lines BL 2 and BL' 3 receives a charge differential representing a data value, such as a logic level low or logic level high, which was stored in and subsequently read from a DRAM cell connected thereto. Bit line pair BL 2 and BL' 3 is suitably associated with two columns of memory cells of a first memory array 4. FIG. 1 illustrates two DRAM storage cells 5 and 6 from first memory array 4 connected to bit line pair BL 2 and BL' 3, respectively. It is understood that a number of DRAM cells of first memory array 4 are connected to each bit line BL 2 and BL' 3. When connected to a sense amplifier 7, the bit lines BL 2 and BL' 3 are selectively driven towards two opposite reference voltage values, such as Vdd and Vss. Pass and/or transmission gates 8 and 9 are connected between bit line pair BL 2 and BL' 3 and sense amplifier 7, respectively, to facilitate the sensing and driving operation of sense amplifier 7. Pass/transmission gates 8 and 9 are activated on or around the time data is provided to one of bit lines BL 2 and BL' 3 due to a memory cell read operation, and remain activated until the accessed memory cell is refreshed. Additional pass/transmission gates 10 and 11 are connected between sense amplifier 7 and another bit line pair associated with a second memory array (not shown).