High speed single-ended amplifier of a latched type

#1. Field of the Invention

#The present invention relates to a memory device, and more particularly to a single-ended bit line structure of latched type, capable of sensing data at a high speed.

#2. Description of Prior Art

#Other objects and aspects of the invention will become apparent from the following description of the embodiments with reference to the accompanying drawings, in which:

#FIG. 1 is a schematic view illustrating a semiconductor memory device (ROM) including a conventional single-ended sense amplifier;

#FIG. 2 is a schematic view illustrating a semiconductor memory device (ROM) including a single-ended sense amplifier in accordance with the present invention; and

#Hereinafter, the present invention will be described below referring to FIGS. 2 to 4.

#First, referring to FIG. 2, a sense amplifier according to the present invention is shown in FIG. 2. Also, shown in FIG. 2 are a core cell area, single-ended bit lines, a single-ended dummy line, a single-ended sense amplifier 100, a reference voltage generator 300, a switching unit 200. The bit lines B0 to Bi and the dummy bit line are precharged by NMOS transistors TR1 in response to a control signal Phi-1# (inversed signal of Phi-1). Also, the bit lines B0 to Bi are selected by NMOS transistors TR2 of which gates are coupled to column selecting signals YA0 to YAi.

#The single-ended sense amplifier 100 according to the present invention is an amplifier of latched type. Accordingly, the memory device according to the present invention includes the single-ended sense amplifier 100 of latched type, which senses the voltage difference between a reference voltage and the bit line voltage during the sensing operation, the reference voltage generator 300 generating the reference voltage for the single-ended sense amplifier 100, and the switching unit 200 separating the single-ended sense amplifier 100 from the output from the bit lines and the reference voltage generator 300.