US 5,963,483 A · Synchronous memory unit

Abstract

A synchronous memory unit which includes a plurality of input buffers for receiving address data, a plurality of input latches for holding and outputting address data from in the input buffers according to a clock signal, a plurality of decoders for decoding the address data from the input latches, and a memory cell array having a plurality of memory cells which store and output data signals via bit lines according to the address data decoded by the decoders. Also provided are a sense amplifier for amplifying the output data signals on the bit lines, a selector for selecting one of the amplified output data signals according to the address data decoded by the decoders, and a selector output latch for holding and outputting the amplified output data signal from the selector according to the clock signal. An output latch holds and outputs the amplified output data signal from the selector output latch according to the clock signal. An output buffer receives and outputs the amplified output data signal from the output latch. Each latch includes a first latch for holding and outputting a data signal according to the clock signal, a first switch connected to the first latch for allowing a data signal to pass to the first latch according to the clock signal, and a second latch for holding and outputting a data signal according to the clock signal, and a second switch, connected between the first and second latches, for allowing a data signal to pass from the first latch to the second latch according to the clock signal.

Claims38

Dependent claims

A synchronous memory unit comprising:

a plurality of input buffers for receiving address data;
a plurality of input latches for holding the address data held in the input buffers and outputting the address data according to a clock signal;
a plurality of decoders for decoding the address data from the input latches;
a memory cell array having a plurality of memory cells which store data signals and output data signals in a predetermined plurality of memory cells via bit lines according to the address data decoded by the decoders;
a sense amplifier for amplifying the output data signals on the bit lines;
a selector for selecting one amplified output data signal from the amplified output data signals from the sense amplifier according to the address data decoded by the decoders;
a selector output latch for holding the amplified output data signal from the selector and outputting the amplified output data signal according to the clock signal;
an output latch for holding the amplified output data signal from the selector output latch and outputting the amplified output data signal according to the clock signal;
and
an output buffer for receiving the amplified output data signal from the output latch and outputting the amplified output data.

7 more elements

A synchronous memory unit comprising:

a plurality of input buffers for receiving address data;
a plurality of input latches for holding the address data held in the input buffers and outputting the address data according to a clock signal;
a plurality of decoders for decoding the address data output from the input latches;
a memory cell array having a plurality of memory cells which store data signals in the memory cells and output data signals in a predetermined plurality of memory cells via bit lines according to the address data decoded by the decoders;
a sense amplifier for amplifying output data signals on the bit lines;
a selector address latch for holding selector address data for selecting one amplified output data signal from the amplified output data signals from the sense amplifier and outputting the selector address data according to the clock signal;
a sense amplifier output latch for holding the amplified output data signals from the sense amplifier and outputting the amplified output data signals according to the clock signal;
a selector for selecting one amplified output data signal from the amplified output data signals held in the sense amplifier output latch based on the selector address data from the selector address latch;
an output latch for holding the amplified output data signals from the selector and outputting the amplified output data signal according to the clock signal;
and
an output buffer for receiving the amplified output data signal from the output latch and outputting the amplified output data signal.

8 more elements

A synchronous memory unit comprising:

a plurality of input buffers for receiving address data;
a plurality of input latches for holding the address data held in the input buffers and outputting the address data according to a clock signal;
a plurality of predecoders for predecoding the address data from the input latches;
a plurality of decoders for decoding the address data predecoded by the predecoders;
a memory cell array having a plurality of memory cells which store data signals and output data signals in a predetermined plurality of memory cells via bit lines according to the address data decoded by the decoders;
a sense amplifier for amplifying the output data signals on the bit lines;
a selector address latch for holding selector address data for selecting one amplified output data signal of the amplified output data signals from the sense amplifier and outputting the selector address data according to the clock signal;
a plurality of selector address decoders for decoding the selector address data from the selector address latch;
a sense amplifier output latch for holding the amplified output data signals from the sense amplifier and outputting the amplified output data signals according to the clock signal;
a selector for selecting one amplified output data signal from the amplified output data signals held in the sense amplifier output latch according to the selector address data decoded by the selector address decoders;
an output latch for holding the amplified output data signal from the selector according to the clock signal;
and
an output buffer for receiving the amplified output data signal from the output latch and outputting the amplified output data signal.

10 more elements

A synchronous memory unit comprising:

a plurality of input buffers for receiving address data;
a plurality of input latches for holding the address data held and outputting the address data according to a clock signal;
a plurality of predecoders for predecoding the address data from the input latches;
a plurality of decoders for decoding the address data predecoded by the predecoders;
a memory cell array having a plurality of memory cells which store data signals and output data signals in a predetermined plurality of memory cells via bit lines according to the address data decoded by the decoders;
a sense amplifier for amplifying the output data signals on the bit lines;
a sense amplifier output latch for holding the output data signals from the sense amplifier;
a selector address latch for holding selector address data for selecting one amplified output data signal from the amplified output data signals from the sense amplifier and outputting the selector address data according to the clock signal;
a plurality of selector address decoders for decoding the selector address data from the selector address latch;
a pulsing circuit for converting the selector address data decoded by the selector address decoders to a pulse;
a selector for selecting one amplified output data signal from the amplified output data signals in the sense amplifier output latch based on the pulsed output from the pulsing circuit;
an output latch for holding the amplified output data signal from the selector and outputting the amplified output data signal according to the clock signal;
and
an output buffer for receiving the amplified output data signal from the output latch and outputting the amplified output data signal.

11 more elements

Dependencies are inferred from the claim text.

Synchronous memory unit

Life of this patent

Synchronous memory unit

Life of this patent

Abstract

Claims38