Memory integrated circuit with shared read/write line

Abstract

A memory device is provided with N>1 memory arrays. Each of the memory arrays comprises a plurality of memory cells arranged into rows and columns. N I/O lines are provided that can be simultaneously activated during a prefetch cycle. Each of the I/O lines is connected to the memory cells of a different one of the N memory arrays for transferring data signals to and from specific addressed ones of the memory cells of the respective memory array. N latches are also provided wherein each of the latches is connected to a different one of the I/O lines. Furthermore, a read/write line is connected to each of the latches and extends along an edge of each memory array. During a prefetch cycle, each of the N I/O lines simultaneously transfers a data signal thereon. Each of the N latches receives a different phase clock signal for synchronizing a transfer of N data signals, including one data signal of each of the latches. The data signals are transferred between the latches and the read/write line so that each data signal is transferred during a respective different n.sup.th interval of a transfer cycle, where 1.ltoreq.n.ltoreq.N. As such, N data signals, including one data signal originating at, or destined to, each of the N memory arrays, are transferred sequentially via the read/write line during the prefetch cycle.

Dependencies are inferred from the claim text.