Flash EPROM erase algorithm with wordline level retry

An apparatus for storing data, comprising:

• a memory array including a plurality of blocks of floating gate memory cells, each of the plurality of blocks including a plurality of wordlines of floating memory cells;
• energizing power supply circuits, coupled with the memory array, to apply energizing voltages to the plurality of blocks of memory cells to read and program addressed memory cells in the memory array and erase at least one of the plurality of blocks;
• erase verify logic, coupled with the memory array, to separately verify erasure of individual wordlines in the plurality of wordlines that compose the at least one of the plurality of blocks;
• and
• control circuits, coupled with the energizing power supply circuits and the erase verify logic, to control the energizing power supply circuits and wherein:
• the control circuits further include i) a plurality of block erase flags corresponding to respective blocks in the plurality of blocks and ii) a plurality of shared wordline erase flags corresponding to respective wordlines in each of the plurality of blocks, the plurality of shared wordline erase flags being shared by each of the plurality of blocks;
• and
• the erase verify logic further includes a circuit responsive to the plurality of shared wordline erase flags to separately verify erasure of individual wordlines indicated by the plurality of shared wordline erase flags.

A FLASH EPROM integrated circuit, comprising:

• a memory array including a plurality of blocks of FLASH EPROM memory cells, each of said plurality of blocks of FLASH EPROM memory cells including a plurality of wordlines of FLASH EPROM memory cells;
• a plurality of block erase flags corresponding to respective blocks in the plurality of blocks of FLASH EPROM memory cells;
• a plurality of shared wordline erase flags corresponding to respective wordlines in the plurality of wordlines of FLASH EPROM memory cells;
• command logic, coupled to command inputs, to set the shared wordline erase flags corresponding to wordlines to be erased;
• energizing power supply circuits, coupled with the memory array, to apply energizing voltages to read and program addressed memory cells in the memory array and to erase wordlines in the memory array;
• erase verify logic coupled with the memory array, for i) separately verifying erasure of wordlines in the plurality of blocks of FLASH EPROM memory cells and ii) resetting the shared wordline erase flags of wordlines which pass erase verify;
• and
• control circuits coupled with the plurality of shared wordline erase flags, the energizing power supply circuits, and the erase verify logic to control the energizing power supply circuits so as to erase wordlines having the shared wordline erase flags set and wherein:
• the erase verify logic further includes a circuit responsive to the plurality of shared wordline erase flags, for verifying erasure of only wordlines having the shared wordline erase flags set.

An apparatus for storing data, comprising:

• a memory array including a plurality of wordlines of FLASH EPROM memory cells;
• energizing power supply circuits, coupled with the memory array, to a) apply energizing voltages to the plurality of wordlines of FLASH EPROM memory cells to read and program addressed memory cells in the memory array and b) erase at least one of the plurality of wordlines of FLASH EPROM memory cells;
• erase verify logic, coupled with the memory array, to separately verify erasure of individual wordlines in the plurality of wordlines of FLASH EPROM memory cells;
• and
• control circuits, coupled to both the energizing power supply circuits and the erase verify logic, to control the energizing power supply circuits, and wherein:
• the control circuits further include a plurality of wordline erase flags corresponding to respective wordlines in the plurality of wordlines of FLASH EPROM memory cells;
• and
• the erase verify logic further includes a circuit responsive to the plurality of wordline erase flags to verify erasure of wordlines indicated by the wordline erase flags.