Fowler-Nordheim (F-N) tunneling for pre-programming in a floating gate memory device

A method for erasing selected blocks of floating gate memory cells in an array including a plurality of blocks, the memory cells in the plurality of blocks being formed in a corresponding channel well within an isolation well in a semiconductor substrate, and wherein the blocks in the plurality of blocks include a plurality of rows and columns of cells in which rows of cells in the block are coupled with corresponding word lines, and columns of cells in the block are coupled with corresponding bit lines, comprising:

• selecting one or more blocks in the plurality of blocks to be erased;
• setting word lines of memory cells in the selected one or more blocks to a pre-program word line potential having a positive value;
• applying a pre-program channel potential having a negative value to the channel well of memory cells in the selected one or more blocks to induce transfer of electrons into the floating gates of cells in the selected one or more blocks from the channel well so that charge levels in the floating gates of memory cells establish a pre-programmed state for the memory cells in the selected one or more blocks;
• removing the pre-programming word line potential from the word lines and removing the pre-program channel potential from the channel well of the selected one or more blocks, and applying a verify potential to word lines corresponding to the plurality of rows in the selected one or more blocks;
• verifying the pre-programming of the selected one or more blocks by sensing at least one bit line at a time corresponding to a column of cells in the plurality of columns to verify that the memory cells in the column and in the plurality of rows in the selected one or more blocks are in the pre-programmed state;
• if cells in the selected one or more blocks do not pass the step of verifying, then retrying the steps of setting, applying, removing and verifying for blocks which do not pass, until all cells in the selected one or more blocks pass the step of verifying or until a retry limit is reached;
• and
• if all cells in the selected one or more blocks pass the step of verifying, then erasing the one or more selected blocks of floating gate memory cells by inducing tunneling of electrons to the channels from the floating gates of the cells to establish an erased state in the cells in the selected one or more blocks.

A method for erasing a block of floating gate memory cells, the respective cells in the block including a drain, a source, a floating gate and a control gate, on a semiconductor substrate having a first conductivity type, the substrate including an isolation well having a second conductivity type different than the substrate, a channel well within the isolation well having the first conductivity type, and source and drain regions for the cells in the block having the second conductivity type within the channel well, the method comprising:

• pre-programming cells in the block by inducing tunneling current between the floating gates and the channel well to pre-program cells in the block by applying respective pre-programming potentials to the control gates, to the channel well, to the isolation well and to the substrate, the pre-programming potentials applied to the control gates and the channel well set to establish an electric field between the control gates and the channel well sufficient to induce tunneling current of electrons into the floating gates, the pre-programming potential applied to the isolation well set so that current between the channel well and the isolation well is blocked, and the pre-programming potential applied to the substrate set so that current between the isolation well and substrate is blocked;
• and
• erasing the cells in the block by inducing tunneling current between the floating gates and the channel well to erase the pre-programmed cells in the block by applying respective erasing potentials to the control gates, to the channel well, to the isolation well and to the substrate, the erasing potentials applied to the control gates and the channel well set to establish an electric field between the control gates and the channel well sufficient to induce tunneling current of electrons out of the floating gates, the erasing potential applied to the isolation well set so that current between the channel well and the isolation well is blocked, and the erasing potential applied to the substrate set so that current between the isolation well and substrate is blocked.