Advanced nonvolatile memories adaptable to dynamic random access memories and methods of operating therein

A nonvolatile memory compatible with a dynamic random access memory, comprising:

• a memory array divided into one or more pairs of mats, each mat including a plurality of sub-array sections separated from each other in a row direction, a plurality of first type section decoders and a plurality of second type section decoders being provided for the respective separated sub-array sections, each of the section decoders being alternately arranged adjacent to one or between two of the sub-array sections to select rows of the adjacent one or two sub-array sections;
• reading and writing row decoders for respectively selecting rows of the memory array during reading and writing operations;
• and
• reading and writing gate drive circuits for respectively selecting a plurality of drive lines which supply source voltages to the rows of the memory array during the reading and writing operations,
• wherein the first type section decoders each selects a half of the rows of the adjacent one or two sub-array sections, the second type section decoders each selects the other rows of the adjacent one or two sub-array sections, and the first type section decoders are respectively opposite to the second type section decoders within each mat pair.

A nonvolatile memory compatible with a dynamic random access memory comprising:

• a memory array divided into at least one pair of mats, each mat including a plurality of sub-arrays arranged in a first direction, each sub-array including a plurality of sub-blocks arranged in a second direction, a number of sub-blocks forming a block in the first direction;
• and
• a plurality of section decoders arranged adjacent to the sub-arrays for connecting drive lines thereto;
• wherein the rows of each sub-array are allocated to more than one adjacent section decoder;
• wherein each sub-aray is arranged between two section decoders such that one of the two section decoders connects drive lines to some of the rows of the sub-array, and the other of the two section decoders connects drive lines to the remaining rows of the sub-array;
• and
• wherein each section decoder that is aranged between two sub-arrays connects drive lines to some of the rows of each of the two adjacent sub-arays.