Semiconductor memory device

A semiconductor memory device comprising:

• a plurality of word lines;
• a pair of bit lines crossing a plurality of said word lines;
• a plurality of memory cells arranged at the crossing points of a plurality of said word lines and one bit line of said pair of bit lines, wherein each memory cell has an information storing capacitor and a selection MOSFET and each selection MOSFET has a source-drain path provided between the corresponding bit line and one electrode of said information storing capacitor and a gate connected to a corresponding word line;
• a sense amplifier connected to said pair of bit lines, wherein said sense amplifier supplies high and low level voltages to said pair of bit lines;
• a plate voltage supply circuit which supplies a plate voltage to the other electrode of said information storing capacitors, wherein said plate voltage supply circuit is formed to set said plate voltage to an intermediate voltage of said high and low level potentials;
• and
• a plate voltage detecting circuit which detects whether said plate voltage has reached a predetermined potential or not after start of operation of said plate voltage supply circuit;
• wherein said information storing capacitor includes a dielectric material film formed of one of a ferro-dielectric material and a high dielectric material, and wherein access to said memory cells is inhibited until said plate voltage reaches said predetermined potential.

A semiconductor memory device comprising:

• a plurality of word lines;
• a pair of bit lines crossing a plurality of said word lines;
• a plurality of memory cells arranged at the crossing points of a plurality of said word lines and one of said pair of bit lines, wherein each memory cell has an information storing capacitor and selection MOSFET and each selection MOSFET has a source-drain path provided between a corresponding bit line and one electrode of said information storing capacitor and a gate connected to a corresponding word line;
• a sense amplifier connected to said pair of bit lines, wherein said sense amplifier supplies high and low level potentials to said pair bit lines;
• a plate voltage supply circuit which supplies a plate voltage to the other electrode of said information storing capacitors, wherein said plate voltage supply circuit is constituted to output a plate voltage which is set to an intermediate potential of said high and low level potentials;
• and
• a timer circuit which measures a predetermined period after the power is turned ON for said semiconductor memory device;
• wherein said information storing capacitor includes a dielectric material film formed of one of a ferro-dielectric material and a high dielectric material, and wherein access to said memory cell is inhibited until the predetermined time period has expired.

A semiconductor device comprising:

• a plurality of word lines;
• a pair of bit lines;
• a plurality of memory cells coupled to one of said plurality of word lines and one of said pair of bit lines, wherein each memory cell has a capacitor and a transistor coupled between one electrode of said capacitor and a corresponding bit line;
• an amplifier coupled to said pair of bit lines, wherein said amplifier operates receiving a first voltage and a second voltage which is larger than said first voltage;
• a voltage supply circuit which supplies a third voltage to the other electrode of said capacitors, wherein said third voltage is larger than said first voltage and lower than said second voltage;
• and
• a timer circuit which measures a predetermined time period after the power for said semiconductor device is turned ON,
• wherein said plurality of word lines are at a non-selecting level until said predetermined time period has expired.

A semiconductor device comprising:

• a plurality of word lines;
• a pair of bit lines;
• a plurality of memory cells coupled to one of said plurality of word lines and one of said pair of bit lines, wherein each memory cell has a capacitor and a MOSFET having a source-drain path provided between a corresponding bit line and one electrode of said capacitor and a gate connected to a corresponding word line;
• an amplifier coupled to said pair of bit lines, wherein said amplifier supplies a first voltage and a second voltage which is larger than said first voltage to said pair of bit lines;
• a voltage supply circuit which supplies a third voltage to the other electrode of said capacitors, wherein said third voltage is larger than said first voltage and lower than said second voltage;
• and
• a timer circuit outputting a control signal, wherein said control signal changes from a first level to a second level when a predetermined time period has expired after said voltage supply circuit is activated,
• wherein said plurality of word lines are at a non-selecting level while said control signal is at said first level.

A semiconductor device comprising:

• a plurality of word lines;
• a pair of bit lines;
• a plurality of memory cells coupled to one of said plurality of word lines and one of said pair of bit lines, wherein each memory cell has a capacitor and a transistor having a current path provided between a corresponding bit line and one electrode of said capacitor;
• an amplifier coupled to said pair of bit lines, wherein said amplifier senses voltage levels of said pair of bit lines and supplies a first voltage and a second voltage which is larger than said first voltage to said pair of bit lines;
• a voltage generating circuit which supplies a third voltage to the other electrode of said capacitors, wherein said third voltage is larger than said first voltage and lower than said second voltage;
• and
• a timer circuit which measures a predetermined period after said voltage generating circuit changes from a non-activating state to an activating state,
• wherein access to said memory cells is inhibited until said predetermined period has expired.