Method and apparatus for efficiently implementing complex function blocks in integrated circuit designs

A method for designing an integrated circuit using a compilation tool, said method comprising:

• (A) developing at least one top-level HDL template and one lower-level HDL template, wherein said top-level template is arranged to call said lower-level template, said template developing including:
• (a) creating said top-level and lower-level HDL templates to serve different functions;
• and
• (b) creating a parameter file and a parameter check file for each of said HDL templates, wherein said parameter file associated with said top-level template is used to create at least one option set;
• (B) developing design specifications for use in a creating HDL for synthesis, wherein a first macro instantiated in said top-level template is compiled with said option set;
• (C) creating said HDL for synthesis;
• and
• (D) creating a netlist for at least one macro block using said design specifications and said HDL templates.

A method for developing an integrated circuit design using a compilation tool, said method comprising:

• (A) developing one or more HDL templates by:
• (a) creating said one or more HDL templates, each template having different functions;
• (b) creating a parameter file and a parameter check file for each of said HDL templates;
• and
• (c) encrypting said HDL templates;
• (B) developing design specifications for use in creating a HDL for synthesis;
• (D) creating said HDL for synthesis by decrypting said encrypted HDL template;
• and
• (E) creating a netlist for at least one macro block using said design specifications and said HDL template.

An integrated circuit design tool comprising:

• a computer system including a central processing unit (CPU) and memory coupled to said CPU;
• means for obtaining at least one HDL template, at least one parameter file, and at least one parameter check file for use in developing design specifications for an integrated circuit design;
• means for developing said design specifications by determining an appropriate macro for use in meeting said design specifications, said means for developing said design specifications further including:
• means for using said parameter file to create a plurality of desired option sets;
• and
• means for compiling said macro using an option set selected from said plurality of desired option sets;
• means for creating a HDL for synthesis using said design specifications and said HDL template;
• and
• means for creating a netlist using said design specifications and said HDL template.

A method for developing an integrated circuit design using a compilation tool, said method comprising:

• (A) developing at least one HDL template by:
• (a) creating said HDL template;
• and
• (b) creating a parameter file and a parameter check file for said HDL template;
• (B) developing design specifications for use in creating a HDL for synthesis;
• (C) creating said HDL for synthesis including:
• (c) encrypting said HDL template;
• (d) decrypting said encrypted HDL template;
• and
• (e) executing said decrypted HDL template;
• and
• (D) creating a netlist for at least one macro block using said design specifications and said HDL template.