Input/output electrostatic discharge protection circuit for an integrated circuit (IC)

Abstract

An input/output electrostatic discharge (ESD) protection circuit for an integrated circuit disposed between an input/output port and the internal circuitry, including an input path protection device and an output path protection device. The output path protection device includes a pair of pull-up and pull-down transistors, two resistors, and a first and a second MOS field effect transistors respectively connected in parallel with the pull-up and the pull-down transistors. The resistors are formed in lightly-doped regions of the source or drain of the pull-up and pull down transistors, respectively, so the series resistance can be reduced efficiently, the driving ability can be prevented from decreasing and the devices can obtain uniform breakdown under intensive layout circumstances. The first and the second MOS field effect transistors are utilized to protect against both positive electrostatic stress and negative electrostatic stress to improve overall ESD protection.

Dependencies are inferred from the claim text.