Delay correction circuit
AssigneeThomson Consumer Electronics, Inc.
InventorGreg Alan Kranawetter
Life of this patent
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Abstract
A delay correction circuit includes a source of a clock signal and a source of a timing signal asynchronous with the clock signal. A timing signal detector is responsive to the clock signal and the timing signal, and is properly operative only when the timing signal is stable for a predetermined time period around the clock signal. A control circuit conditions utilization circuitry to operate after a delay time after the timing signal is detected. Adjusting circuitry conditions the control circuit to adjust the delay time if the timing signal was not stable within the predetermined time period.
Claims11
A delay correction circuit, comprising:
- a source of a clock signal;
- a source of a timing signal asynchronous with the clock signal;
- a timing signal detector, responsive to the clock signal and the timing signal, and properly operative only when the timing signal is stable for a predetermined time period around the clock signal;
- a control circuit for conditioning utilization circuitry to operate after a delay time after the timing signal is detected;
- and
- an adjusting circuit for conditioning the control circuit to adjust the delay time if the timing signal was not stable within the predetermined time period.
A delay correction circuit, comprising:
- a source of a composite video signal including a horizontal synchronization signal component;
- a source of a burst locked clock, synchronized to the composite video signal, and having successive cycles, each cycle having a leading edge and a trailing edge;
- a circuit for detecting the horizontal synchronization signal at a leading edge of the burst locked clock signal;
- a circuit for detecting the horizontal synchronization signal at a trailing edge of the burst locked clock signal;
- a circuit for measuring the skew between the horizontal synchronization signal and the leading edge of an adjacent cycle of the burst locked clock;
- a correction logic circuit, for generating an increment signal when the skew is less than a predetermined minimum and the horizontal synchronization signal is detected at a leading edge of the burst locked clock signal, and for generating a decrement signal when the skew is greater than a predetermined maximum and the horizontal synchronization signal is detected at a trailing edge of the burst locked clock signal;
- and
- a memory control circuit, for delaying:
- one more than a predetermined number of cycles of the burst locked clock signal in response to the increment signal;
- one less than the predetermined number of cycles of the burst locked clock signal in response to the decrement signal;
- and
- the predetermined number of clock cycles otherwise, then storing successive samples representing the composite video signal in a frame store.
Dependencies are inferred from the claim text.