US 5,963,222 A · Multi-format reduced memory MPEG decoder with hybrid memory address generation

Abstract

An address generation engine is disclosed for a digital video decoder unit coupled to memory in a digital video decoder system wherein the memory accommodates multi-format and/or reduced video data storage. The address generation engine includes a processor and address generation hardware. The processor, coupled to access encoded data to be decoded by the digital video decoder unit, has microcode for deriving from the encoded data relative location information including a vertical component and a horizontal component. The address generation hardware includes a row address register and a column address register for receiving the vertical component and horizontal component, respectively, derived by the processor. The address generation hardware is configured for generating from the vertical component and the horizontal component either a macroblock write address for writing a reconstructed macroblock of data to memory, a motion compensation read address for accessing pertinent motion vector information of the encoded data for reconstructing the macroblock, and a pan and scan offset address usable by a display unit for displaying reconstructed video data in pan and scan format.

Claims28

Dependent claims

An address generation engine for a digital video decoder unit coupled to memory, said address generation engine comprising:

a processor coupled to access an encoded video signal to be decoded by said digital video decoder unit, said processor having microcode for deriving from said encoded video signal relative location information including a vertical component and a horizontal component;
and
address generation hardware including a row address register and a column address register for receiving the vertical component and horizontal component, respectively, of said relative location information derived by said processor, said address generation hardware being coupled to and initiated by said processor and being configured to generate from said vertical component and horizontal component at least one of a macroblock write address, a motion compensation read address, and a pan and scan offset address, wherein said at least one of said macroblock write address, said motion compensation read address and said pan and scan offset address is generated in hybrid fashion using said microcode of said processor and said address generation hardware.

A digital video decoder system for decoding an encoded digital video signal, said system comprising:

memory and a memory controller for temporarily storing the encoded digital video signal;
a variable length code (VLC) decoder coupled to said memory for decoding encoded data of the encoded digital video signal, thereby producing decoded data;
an inverse quantizer (IQ) coupled to the VLC decoder for dequantizing the decoded data to produce therefrom dequantized, decoded data;
a discrete cosine transform inverter (IDCT) coupled to the IQ for transforming the dequantized, decoded data from frequency domain to spatial domain, said spatial domain, dequantized decoded data including difference data;
a motion compensator (MC) and adder for receiving reference data from said memory and said difference data from the IDCT to form motion compensated pictures therefrom;
and
a hybrid address engine coupled to said MC and to a display unit of said digital video decoder system for providing addressing to said memory, said hybrid address engine comprising:
a processor coupled to memory to access the encoded data to be decoded, said processor having microcode for deriving from said encoded data relative location information including a vertical component and a horizontal component;
and
address generation hardware including a row address register and a column address register for receiving the vertical component and horizontal component, respectively, determined by said processor, said address generation hardware being coupled to and initiated by said processor and being configured to generate from said vertical component and horizontal component at least one of a macroblock write address, a motion compensation read address and a pan and scan offset address, wherein said at least one of said macroblock write address, said motion compensation read address and said pan and scan offset address is generated in hybrid fashion using said microcode of said processor and said address generation hardware.

7 more elements

In a digital video decoder system for decoding an encoded video signal, a hybrid address generation method for use within a digital video decoder unit for addressing memory of the digital video decoder system, said method comprising:

using microcode of a processor, coupled to access encoded data to be decoded by the digital video decoder unit, to generate therefrom relative location information including a vertical component and a horizontal component;
and
using address generation hardware coupled to the processor to generate from said vertical component and said horizontal component at least one of a macroblock write address, a motion compensation read address, and a pan and scan offset address, wherein said at least one of said macroblock write address, said motion compensation read address and said pan and scan offset address is generated in hybrid fashion using said microcode of said processor and said address generation hardware.

Dependencies are inferred from the claim text.

Multi-format reduced memory MPEG decoder with hybrid memory address generation

Life of this patent

Multi-format reduced memory MPEG decoder with hybrid memory address generation

Life of this patent

Abstract

Claims28