US 5,963,200 A · Video frame synchronization of independent timing generators for frame buffers in a master-slave configuration

Abstract

A method and apparatus for synchronizing the vertical blanking of multiple frame buffers which may exist on the same computer or separate computers for certain applications including stereo display, virtual reality and video recording, which require such synchronization. To obtain the required synchronization one frame buffer is designation as the master. It provides a signal called FIELD that changes state (0 to 1 or 1 to 0) at the start of every vertical sync event on the master frame buffer. All other frame buffers are set to be slaves. Their timing generators sample the master's FIELD signal. When they detect the master's FIELD signal changing state, they set their own internal timing to match to thereby achieve frame synchronization.

Claims13

Dependent claims

An apparatus for synchronizing a vertical blanking signal for each of a plurality of independent frame buffers comprising:

a plurality of RAMDACs, each for coupling to a corresponding rendering controller and a display monitor which receives video signals, wherein one of said plurality of RAMDACs operates as a master and each of the other of said plurality of RAMDACs operates as a slave, each of said RAMDACS including logic which generates a vertical blanking signal, each of said slave RAMDACs including reset logic which generates a signal which resets said vertical blanking signal logic;
wherein said RAMDAC operating as a master further comprises a field signal generator which generates a field signal which is provided to each of said plurality of RAMDACs operating as a slave, and each of said slave RAMDACs upon receipt of said field signal operates said reset logic to thereby synchronize the video signals provided to its corresponding display monitor.

A method for synchronizing a vertical blanking signal for each of a plurality of independent frame buffers comprising the steps of:

a) designating one of a plurality of RAMDACs, each for coupling to a corresponding rendering controller and a display monitor which receives video signals, as a master and designating each of the other of said plurality of RAMDACs as a slave;
b) generating a vertical blanking signal for each of said plurality of independent frame buffers;
c) synchronizing the video signals provided to the display monitor coupled to each of said plurality of RAMDACs by generating a field signal which is provided to each of said plurality at RAMDACs operating as a slave, said slave RAMDACs, upon receipt of said field signal, operating to reset logic used for generating the vertical blanking signal to thereby synchronize the video signals to be provided to its corresponding display monitor.

Dependencies are inferred from the claim text.

Video frame synchronization of independent timing generators for frame buffers in a master-slave configuration

Life of this patent

Video frame synchronization of independent timing generators for frame buffers in a master-slave configuration

Life of this patent

Abstract

Claims13