Double-sided pulse width modulator

A double-sided pulse width modulator comprising:

• an amplifier having a first input, a second input, and an output, said first input connected to a first reference potential;
• a first bank of storage elements, each of said storage elements having a first terminal connected to said second input of said amplifier, and a second terminal;
• a first bank of switches, each switch in said first bank of switches having an output terminal connected to a second terminal of said storage elements, an input terminal, and a control terminal connectable by a timing gate to an output of said modulator and a polarity control bit for a first value to be input into said input terminals;
• a feedback storage element connected in parallel with a first timing switch between said second input of said amplifier and said output of said amplifier;
• a comparator having a first input connected to a second reference potential, a second input, a timing enable input, and an output;
• a second bank of storage elements, each of said storage elements having a first terminal connected to said second input of said comparator, and a second terminal;
• a second timing switch connected between said output of said amplifier and said second input of said comparator;
• a second bank of switches each of said switches having a first terminal connected to one of said storage elements in said second bank of storage elements, a second terminal connected to said output of said amplifier, and a control terminal connected to a second value;
• and
• a current source connected to said second input of said comparator, said current source discharging a value having a duration proportional to the product of said first input value and said second input value to form said output of said modulator at said output of said comparator.

A double-sided pulse width modulator comprising:

• an amplifier having a first input, a second input, and an output, said first input connected to a first reference potential;
• a first bank of storage elements, each of said storage elements having a first terminal connected to said second input of said amplifier, and a second terminal;
• a first bank of switches, each switch in said first bank of switches having an output terminal connected to a second terminal of said storage elements, an input terminal, and a control terminal connectable by a timing gate to an output of said modulator and a polarity control bit for a first value to be input into said input terminals;
• a feedback storage element connected in parallel with a first timing switch between said second input of said amplifier and said output of said amplifier;
• a comparator having a first input connected to a second reference potential, a second input, a timing enable input, and an output;
• a second bank of storage elements, each of said storage elements having a first terminal connected to said second input of said comparator, and a second terminal;
• a second timing switch connected in parallel with a first one of said storage elements of said second bank of storage elements between said output of said amplifier and said second input of said comparator;
• and
• a current source connected to said second input of said comparator, said current source discharging a value having a duration proportional to the first input value to form said output of said modulator at said output of said comparator.