US 5,963,085 A · Input to output stage interface with virtual ground circuitry for rail to rail comparator

Abstract

An interface stage for interfacing between input and output stages of a rail to rail comparator. The interface stage combines and amplifies four input stage output currents from the input stage, including by common base feeding them to a symmetrical set of virtual grounds, to generate a differential output signal for driving the output stage. In preferred embodiments, the interface stage includes two sets of bipolar transistors, each set connected in a common base configuration, which amplify each input stage output current and assert the resulting amplified signals to a pair of symmetrical virtual ground circuits. Each virtual ground circuit comprises a bipolar transistor and is configured to combine two of the amplified signals to generate one component of the differential output signal. By employing the virtual ground circuits, the slew rate of the interface stage is principally determined by its input transconductance and the collector-to-base stray capacitance of the bipolar transistors of the virtual ground circuits. Thus, since the virtual ground circuits can be implemented with minimum geometry bipolar transistors having very low collector-to-base stray capacitance, the interface stage can be implemented to have very high slew rate. In other embodiments, the invention comprises a rail to rail comparator input stage (having an autozero switch) coupled with an interface stage including autozero circuitry. The autozero circuitry and the autozero switch can be controlled to execute an autozero operation in which DC noise due to offset in the output signal (of the combined input and interface stage) is rapidly attenuated by means of a negative feedback loop.

Claims24

Dependent claims

An interface stage suitable for interfacing between an input stage of a rail to rail comparator and an output stage of the rail to rail comparator, said interface stage comprising:

a top rail and a bottom rail, connectable to a source of operating power;
first amplifier circuitry connected to the top rail and comprising a set of bipolar PNP transistors connected in a common base configuration and configured to amplify a first input current from the input stage and a second input current from the input stage to generate a first set of amplified currents;
second amplifier circuitry connected to the bottom rail and comprising a set of bipolar NPN transistors connected in a common base configuration and configured to amplify a third input current from the input stage and a fourth input current from the input stage to generate a second set of amplified currents;
first virtual ground circuitry coupled between the first amplifier circuitry and the second amplifier circuitry, and configured to assert to a first output node a first output potential indicative of a first linear combination of a subset of the first set of amplified currents and a subset of the second set of amplified currents;
and
second virtual ground circuitry coupled between the first amplifier circuitry and the second amplifier circuitry, and configured to assert to a second output node a second output potential indicative of a linear combination of another subset of the first set of amplified currents and another subset of the second set of amplified currents,
wherein the first input current, the second input current, the third input current, and the fourth input current are together indicative of a differential input signal, and the first output potential and the second output potential comprise a differential output signal indicative of the differential input signal and suitable for driving the output stage.

4 more elements

Circuitry for amplifying a differential input signal, to generate a differential output signal indicative of the differential input signal and suitable for driving an output stage of a rail to rail comparator, said circuitry comprising:

a top rail and a bottom rail connectable to a source of operating power;
an input stage, including an NMOS transistor differential amplifier coupled to the bottom rail and configured to receive the differential input signal and assert a first current and a second current in response to the differential input signal, and a PMOS transistor differential amplifier coupled to the top rail and configured to receive the differential input signal and assert a third current and a fourth current in response to said differential input signal, wherein the first current, the second current, the third current, and the fourth current are together indicative of the differential input signal;
and
an interface stage, said interface stage including:
first amplifier circuitry connected to the top rail and comprising a set of bipolar PNP transistors connected in a common base configuration and configured to receive and amplify the first current and the second current from the input stage to generate a first set of amplified currents;
second amplifier circuitry connected to the bottom rail and comprising a set of bipolar NPN transistors connected in a common base configuration and configured to receive and amplify the third current and the fourth current from the input stage to generate a second set of amplified currents;
first virtual ground circuitry coupled between the first amplifier circuitry and the second amplifier circuitry, and configured to assert to a first output node a first output potential indicative of a first linear combination of a subset of the first set of amplified currents and a subset of the second set of amplified currents;
and
second virtual ground circuitry coupled between the first amplifier circuitry and the second amplifier circuitry, and configured to assert to a second output node a second output potential indicative of a linear combination of another subset of the first set of amplified currents and another subset of the second set of amplified currents, wherein the first output potential and the second output potential comprise said differential output signal.

6 more elements

Circuitry for amplifying a differential input signal to generate a differential output signal indicative of the differential input signal, wherein the differential output signal is suitable for driving an output stage of a rail to rail comparator, and the differential input signal comprises a first potential and a second potential, said circuitry comprising:

a top rail and a bottom rail connectable to a source of operating power;
an input stage, including an NMOS transistor differential amplifier coupled to the bottom rail and configured to receive the differential input signal and assert a first current and a second current in response to the differential input signal, and a PMOS transistor differential amplifier coupled to the top rail and configured to receive the differential input signal and assert a third current and a fourth current in response to said differential input signal, wherein the first current, the second current, the third current, and the fourth current are together indicative of the differential input signal, the NMOS transistor differential amplifier has a first input coupled to receive the first potential and a second input coupled to receive the second potential, the PMOS transistor differential amplifier has a third input coupled to receive the first potential and a fourth input coupled to receive the second potential, and wherein the input stage also includes an autozero switch between the first input and the third input, said autozero switch being configured to enter a closed configuration connecting the first input to the third input in response to a control signal having a first value;
and
an interface stage, the interface stage including:
first amplifier circuitry connected to the top rail and comprising a set of bipolar transistors configured to receive and amplify the first current and the second current from the input stage to generate a first set of amplified currents;
second amplifier circuitry connected to the bottom rail and comprising a second set of bipolar transistors configured to receive and amplify the third current and the fourth current from the input stage to generate a second set of amplified currents;
first virtual ground circuitry coupled between the first amplifier circuitry and the second amplifier circuitry, and configured to assert to a first output node a first output potential indicative of a first linear combination of a subset of the first set of amplified currents and a subset of the second set of amplified currents;
second virtual ground circuitry coupled between the first amplifier circuitry and the second amplifier circuitry, and configured to assert to a second output node a second output potential indicative of a linear combination of another subset of the first set of amplified currents and another subset of the second set of amplified currents;
and
autozero circuitry coupled to the first output node, the second output node, and the first amplifier circuitry, wherein the autozero circuitry is configured to execute an autozero operation in response to said control signal having the first value, wherein the autozero circuitry attenuates DC noise, due to offset, in the differential output signal by means of a negative feedback loop.

7 more elements

Dependencies are inferred from the claim text.

Input to output stage interface with virtual ground circuitry for rail to rail comparator

Life of this patent

Input to output stage interface with virtual ground circuitry for rail to rail comparator

Life of this patent

Abstract

Claims24