Circuit arrangement having at least two signal paths

Abstract

A circuit arrangement having at least two signal paths which can be alternately enabled by feeding respective controllable current sources and by logic signals selecting one of these controllable current sources, while, at a transition from one signal path to the other, the controllable current sources of the relevant two signal paths are controllable by a time-continuously changing control signal during a transition interval, such that currents which can be supplied by these two controllable current sources change continuously and in opposite directions. The object of implementing this circuit arrangement in such a way that the number of components is noticeably reduced in a device enabling a gradual transition from one setting position to the next is achieved with a selection circuit (1) having a control stage (11; 21; 31; 41; 51) for each signal path (T18,T19; T28,T29; T38,T39; T48,T49; T58,T59), each control stage (11; 21; 31; 41; 51) including: an analog multiplexer branch (T11,R1; T21,R2) through which a current can be passed which enables the controllable current source (I1; I2; I3; I4; I5) associated with the relevant signal path (T18,T19; T28,T29; T38,T39; T48,T49; T58,T59), said current being supplied from a reference current source (Iref) which is common to the multiplexer branches (T11,R1; T21,R2) of all control stages (11; 21; 31; 41; 51), a bistable stage (T14,T16,I11,I12; T24,T26,I21,I22) for continuously controlling the current in the multiplexer branch (T11,R1; T21,R2) in accordance with the control signal (UTR) and for storing the state of operation, achieved at the end of the transition interval (t3-t5), of the multiplexer branch (T11,R1; T21,R2) outside the transition interval (t3-t5), and a switching stage (I13,T15; I23,T25) for applying the control signal (UTR) during the transition interval (t3-t5), by the logic signals (s1; s2; s3; s4; s5) and via the bistable stage (T14,T16,I11,I12; T24,T26,I21,I22), to the multiplexer branch (T11,R1; T21,R2) of that signal path (T18,T19; T28,T29; T38,T39; T48,T49; T58,T59, respectively) which is to be enabled in accordance with the logic signals (s1; s2; s3; s4; s5) after termination (t5) of the transition interval (t3 to t5).

Dependencies are inferred from the claim text.