US 5,963,080 A · Undershoot hardened FET switch

Abstract

A bus switch for transferring logic signals between nodes without the problems associated with undershoot conduction. The bus switch is an FET switch including a single primary transfer transistor. The bulk of the transfer transistor is coupled to a bulk regulating circuit including a pseudo low-potential power rail. The pseudo low-potential rail is coupled to one arbiter circuit associated with one of the two circuit transfer nodes and a second arbiter circuit associated with the other of the two transfer nodes. The arbiter circuits are coupled to their respective nodes or pads and to a common low-potential supply rail. The arbiter selects for coupling to the pseudo low-potential rail the signal of the lower potential between that at the pad and that of the low-potential rail. This arrangement ensures that there will be no parasitic conduction of the transfer transistor during undershoot conditions. In an alternative embodiment that may be used to minimize the vagaries associated with process variations, the transfer transistor's gate may be independently coupled to a second pseudo low-potential power rail.

Claims16

Dependent claims

An undershoot-hardened bus switch for regulating a transfer of a logic signal between a first node and a second node, wherein the logic signal is transferred from the first node to the second or from the second node to the first, said bus switch comprising:

a. an enable signal node for receiving a bus switch activation signal;
b. a MOS transfer transistor having a gate coupled to said enable signal node, a source coupled to the first node, and a drain coupled to the second node;
c. a first arbiter circuit having a first input coupled to the first node and a second input coupled to a low-potential power rail;
d. a second arbiter circuit having a first input coupled to the second node and a second input coupled to said low-potential rail;
and
e. a pseudo low-potential power rail coupled to said output of said first arbiter circuit, to said output of said second arbiter circuit, and to a bulk region of said transfer transistor.

3 more elements

a. an enable signal node for receiving a bus switch activation signal;
b. a MOS transfer transistor having a gate coupled to said enable signal node, a source coupled to the first node, and a drain coupled to the second node;
c. a first arbiter circuit having a first input coupled to the first node and a second input coupled to a low-potential power rail;
d. a second arbiter circuit having a first input coupled to the second node and a second input coupled to said low-potential rail;
e. a third arbiter circuit having a first input coupled to the first node and a second input coupled to a low-potential power rail;
f. a fourth arbiter circuit having a first input coupled to the second node and a second input coupled to said low-potential rail;
g. a first pseudo low-potential power rail coupled to said output of said first arbiter circuit, to said output of said second arbiter circuit, and to a bulk region of said transfer transistor;
and
h. a second pseudo low-potential power rail coupled to said output of said third arbiter circuit, to said output of said fourth arbiter circuit, and to a gate of said transfer transistor.

6 more elements

Dependencies are inferred from the claim text.

Undershoot hardened FET switch

Life of this patent

Undershoot hardened FET switch

Life of this patent

Abstract

Claims16