Auto mode selector
AssigneeHyundai Electronics Industries Co., Ltd.
InventorJung Pill Kim
Life of this patent
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Abstract
An auto mode selector for a semiconductor memory device having a reference voltage selection switching circuit connected between a reference voltage pin and an internal reference voltage terminal, for selecting one of CTT and LVTTL in response to a reference voltage selection signal. The auto mode selector further includes an input leakage current controller for allowing current to flow through a resistor between a supply voltage source and the reference voltage pin only for a predetermined time period in response to an input leakage current control signal from an input leakage current control signal generator. According to the present invention, the amount of input leakage current and standby current can be reduced.
Claims6
An auto mode selector for a semiconductor memory device having reference voltage selection switching means connected between a reference voltage pin and an internal reference voltage terminal, for selecting one of CTT and LVTTL in response to a reference voltage selection signal, wherein the improvement comprises input leakage current control means for allowing current to flow through a resistor between a supply voltage source and said reference voltage pin only for a predetermined time period in response to an input leakage current control signal from input leakage current control signal generation means wherein said input leakage current control signal generation means includes:
- a first inverter for inverting a pulse signal from pulse generation means;
- first flip-flop means for latching a twice-inverted power-up signal in response to an output signal from said first inverter;
- a second inverter for inverting said twice-inverted power-up signal;
- a third inverter for inverting an output signal from said first flop-flop means;
- and
- a NOR gate for performing a NOR operation with respect to output signals from said second and third inverters and outputting the NORed result as said input leakage current control signal.
An auto mode selector for a semiconductor memory device having reference voltage selection switching means connected between a reference voltage pin and an internal reference voltage terminal, for selecting one of CTT and LVTTL in response to a reference voltage selection signal, wherein the improvement comprises input leakage current control means for allowing current to flow through a resistor between a supply voltage source and said reference voltage pin only for a predetermined time period in response to an input leakage current control signal from input leakage current control signal generation means wherein said input leakage current control means includes a MOS transistor connected between said supply voltage source and said resistor and having its gate for inputting said input leakage current control signal from said input leakage current control signal generation means wherein said input leakage current control signal generation means includes:
- a first inverter for inverting a pulse signal from pulse generation means;
- first flip-flop means for latching a twice-inverted power-up signal in response to an output signal from said first inverter;
- a second inverter for inverting said twice-inverted power-up signal;
- a third inverter an output signal from said first flip-flop means;
- and
- a NOR gate for performing a NOR operation with respect to output signals from said second and third inverters and outputting the NORed result as said input leakage current control signal.
An auto mode selector for a semiconductor memory device having reference voltage selection switching means connected between a reference voltage pin and an internal reference voltage terminal, for selecting one of CTT and LVTTL in response to a reference voltage selection signal,
- wherein the improvement comprises input leakage current control means for allowing current to flow through a resistor between a supply voltage source and said reference voltage pin only for a predetermined time period in response to an input leakage current control signal from input leakage current control signal generation means, and
- wherein the predetermined time period is between the time when a powerup signal which indicates the timing of a turned-on state of a supply voltage source is activated and the time when a mode register set signal which indicates an operating mode of the semiconductor memory device is activated.
Dependencies are inferred from the claim text.