Circuit with hot-electron protection and method

A circuit comprising:

• a first transistor and a second transistor, each having a first electrode and a second electrode and a control electrode, said first transistor and said second transistor being serially coupled across their first and second electrodes between a node and a ground reference line for pulling said node to said ground reference line, said first transistor being conductive or substantially not conductive in response to a first control signal, said first control signal being related to a first signal;
• said second transistor being conductive with a first, conductivity or with a second conductivity, lower than said first conductivity, in response to a second control signal;
• a control circuit receiving said first signal and providing said second control signal which causes in a first case said first conductivity of said second transistor when said first signal makes said first transistor fully conductive, and which in a second case causes said second conductivity of said second transistor responsive to said first transistor and said second transistor having pulled said node to said ground reference line, thereby in said second case equalizing the voltages across said first electrodes and said second electrodes of said first transistor and said second transistor so that said circuit can accommodate said first signal at said first level which is higher than the maximum allowable voltages across said first and second main electrodes of said first transistor or said second transistor;
• and
• a logic circuit providing said first control signal, said logic circuit having a first input coupled to an input terminal for receiving said first signal and an output for providing said first control signal, said logic circuit comprising a first pull-up transistor having first and second main electrodes coupled between a first reference line and said output, and wherein said control circuit providing said second control signal comprises a second pull-up transistor having first and second main electrodes coupled between said first reference line and the control input of said second transistor.

A circuit comprising:

• a first transistor and a second transistor, each having a first electrode and a second electrode and a control electrode, said first transistor and said second transistor being serially coupled across their first and second electrodes between a node and a ground reference line for pulling said node to said ground reference line, said first transistor being conductive or substantially not conductive in response to a first control signal, said first control signal being related to a first signal;
• said second transistor being always conductive with a first, high conductivity or with a second conductivity, lower than said first conductivity, in response to a second control signal;
• a control circuit receiving said first signal and providing said first control signal and said second control signal which in a first case causes said first conductivity of said second transistor when said first signal makes said first transistor fully conductive, and which in a second case causes said second conductivity of said second transistor responsive to said first transistor and said second transistor having pulled said node to said ground reference line, thereby in said second case equalizing the voltages across said first electrodes and said second electrodes of said first transistor and said second transistor so that said circuit can accommodate said first signal at said first level which is higher than the maximum allowable voltages across said first and second main electrodes of said first transistor or said second transistor;
• and
• a retention circuit having a third transistor and a fourth transistor serially coupled between said node and a ground reference line for keeping said node at said ground reference line, said retention circuit receiving said first signal with a delay, a control electrode of said fourth transistor being coupled to a second reference line.

A method for pulling a node to a ground reference potential by serially coupled first and second transistors, said first transistor being coupled to said ground reference potential and said second transistor being coupled to said node,

• said method comprising the following steps:
• increasing the conductivity of said second transistor from low to high, wherein said second transistor is always being conductive;
• and
• making said first transistor conductive, whereby voltages across main electrodes of said first transistor and said second transistor each remain below a maximum allowable voltage for each transistor.

A circuit comprising:

• a first transistor and a second transistor being serially coupled between a node and a ground reference line, said first transistor being connected to said ground reference line and said second transistor being connected to said node, said first transistor and said second transistor having variable conductivities, said first transistor changing between being conductive or substantially not conductive in response to a first signal, said second transistor being always conductive and changing between having high or low conductivity;
• and
• a control circuit alternatively causing that the conductivity of said second transistor increases from low conductivity to high conductivity when said first signal makes said first transistor conductive;
• and causing that the conductivity of said second transistor decreases from high conductivity to low conductivity when said first signal makes said first transistor non conductive.