US 5,963,074 AGranted

Programmable delay circuit having calibratable delays

AssigneeCredence Systems Corporation

InventorBrian J. Arkin

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Abstract

A programmable delay circuit produces an OUTPUT signal following an INPUT signal with a delay selected by input delay selection data. The delay circuit includes a tapped delay line, a multiplexer, a delay adjustment stage and a programmable encoder. The delay line includes a set of N delay elements connected in series for successively delaying the INPUT signal to produce a set of N output TAP signals. The multiplexer passes a selected TAP signal to the delay adjustment stage. The delay adjustment stage delays the selected TAP signal to produce the OUTPUT signal. The programmable encoder encodes the input delay selection data to provide signals for controlling the multiplexer and for adjusting the delay of the delay adjustment stage. The manner in which the encoder encodes each separate delay selection data value is adjustable so that each of the N selectable delays can be separately calibrated.

Claims12

Dependent claims

A programmable delay circuit for producing a FIRST OUTPUT signal in delayed response to an INPUT signal, wherein said FIRST OUTPUT signal lags said INPUT signal with a circuit delay referenced by input delay selection data, the delay circuit comprising:

encoding means for receiving and encoding said input delay selection data to produce output COARSE data and FINE data, said COARSE data indicating a first delay and said FINE data indicating a second delay, wherein values of COARSE and FINE data produced by said encoding means in response to each value of input delay selection data are determined by programming data provided as input to said encoding means;
first delay means for receiving said INPUT signal and for producing in response thereto a succession of TAP signals;
multiplexing means for receiving said TAP signals, for receiving said COARSE data from said encoding means and for producing a SECOND OUTPUT signal in response to one of said TAP signals selected in accordance with a value of said COARSE data such that said SECOND OUTPUT signal lags said INPUT signal by said first delay;
and
second delay means for receiving said FINE data, for receiving said SECOND OUTPUT signal and for producing said FIRST OUTPUT signal in response to said SECOND OUTPUT signal after said second delay of duration controlled by said FINE data.

2 more elements

Dependencies are inferred from the claim text.