Frequency doubler with adjustable duty cycle

A frequency doubler with an adjustable duty cycle, comprising:

• a reference-clock input terminal for receiving a reference input signal at a reference frequency .function..sub.IN and with a 50 percent duty cycle;
• a variable delay circuit for providing a variable delay to the reference input signal, wherein the variable delay circuit has an input terminal coupled to the reference-clock input terminal, an output terminal, and a control terminal for receiving a control signal for controlling the amount of delay through the variable delay circuit;
• a combining circuit using exclusive logic for logically combining the reference input signal with the delayed reference input signal to provide an output signal at an output terminal wherein the frequency of the output signal is at twice the frequency of the reference input signal;
• and
• a control signal generator circuit having an input terminal coupled to the output terminal of the combining circuit through an average-value circuit, having another input terminal coupled to a DC reference voltage from a DC reference source, and having an output terminal coupled to the control terminal of the variable delay circuit for the control signal which controls the amount of delay through the adjustable delay circuit, wherein the control signal generator compares the average value of the output signal at twice the frequency of the reference input signal to the DC reference voltage to provide the control signal for controlling the amount of delay through the variable delay circuit and wherein the duty cycle of the output signal is determined by the DC reference voltage.

A frequency tripler with an adjustable duty cycle, comprising:

• a reference-clock input terminal for receiving a reference input signal at a reference frequency .function..sub.IN and with a 50 percent duty cycle;
• a first variable delay circuit for providing a first delayed reference input signal;
• a second variable delay circuit for providing a second delayed reference input signal;
• wherein each of the variable delay circuits has an input terminal and a control terminal for receiving a control signal for controlling the amount of delay through each of the first and the second variable delay circuits;
• a combining circuit for logically combining the reference input signal, the first delayed reference input signal, and the second delayed input signal to provide an output signal at an output terminal which output signal has a frequency three times the frequency of the reference input signal;
• a control signal generator circuit having an input terminal coupled to the output terminal of the combining circuit through an average-value circuit, having another input terminal coupled to a DC reference voltage from a DC reference source, and having an output terminal coupled to the control terminals of the variable delay circuits for receiving the control signal which controls the amount of delay through the variable delay circuits, wherein the control signal generator compares the average value of the output signal of the combining circuit at three times the frequency of the reference input signal to the DC reference voltage to provide the control signal for controlling the amount of delay through the adjustable delay circuit;
• and
• wherein the DC reference voltage determines the duty cycle of the output signal.

A frequency multiplier which provides an output signal which has a frequency which is N times the frequency of an input signal and which has an adjustable duty cycle, comprising:

• a reference-clock input terminal for receiving a reference input signal at a reference frequency .function..sub.IN and with a 50 percent duty cycle;
• a plurality of (N-1) variable delay circuits for providing a plurality of progressively delayed reference input signals at respective output terminals;
• wherein each of the variable delay circuits has an input terminal communicatively coupled to said reference input signal and a control terminal for receiving a control signal for controlling the amount of delay through each of the variable delay circuits;
• a combining circuit for logically combining the reference input signal, and the plurality of progressively delayed reference input signals to provide an output signal at an output terminal of the combining circuit which has a frequency N times the frequency of the reference input signal;
• a control signal generator circuit which has an input terminal coupled to the output terminal of the combining circuit through an average-value circuit, having another input terminal coupled to a DC reference voltage from a DC reference source, and which has an output terminal coupled to the control terminals of the variable delay circuits for providing the control signal which control the amount of delay through the variable delay circuits, wherein the control signal generator compares the average value of the output signal of the combining circuit at N times the frequency of the reference input signal to the DC reference voltage to provide the control signal for controlling the amount of delay through the adjustable delay circuits;
• and
• wherein the DC reference voltage determines the duty cycle of the output signal.