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US 5,963,070 AGranted
Stretch cycle generator
AssigneeAdvanced Micro Devices, Inc.
InventorsDarren R. Faulkner, Gregory A. Constant
Life of this patent
Estimating the term…
Abstract
A clock generating circuit includes a clock generator and a cycle controller. The clock generator is coupled to receive a reference oscillating signal. The clock generator provides a clock signal responsive to the reference oscillating signal. The cycle controller is coupled to provide a cycle control signal to the clock generator. The clock generator stretches a cycle of the clock signal responsive to a first value of the cycle control signal.
Claims18
A clock generating circuit comprising:
- a clock generator coupled to receive a reference oscillating signal, the clock generator providing a clock signal responsive to the reference oscillating signal;
- and
- a stretch cycle controller coupled to receive the reference oscillating signal and coupled to provide a cycle control signal to the clock generator, the clock generator stretching a cycle of the clock signal responsive to a value of the cycle control signal to generate a clock signal stretch cycle;
- wherein
- the clock generator comprises:
- a state counter for generating a repeating sequence of states;
- and
- a state decoder for providing the clock signal, the clock signal being determined by the states of the state counter and the cycle control signal;
- the state counter is coupled to provide a plurality of state lines to the state decoder, each state line corresponding to one of the states of the state counter;
- the state decoder includes
- a combination circuit for combining the state lines to generate a plurality of combined state signals, the plurality of combined state signals including
- a first combined state signal providing a normal operation clock signal, and
- a second combined state signal providing a stretched clock signal including the clock signal stretch cycle;
- and
- a selection circuit for selecting one of the first and second combined state signals to provide the clock signal.
12 more elements
A clock generating circuit comprising:
- a clock generator coupled to receive a reference oscillating signal, the clock generator providing a clock signal responsive to the reference oscillating signal;
- and
- a stretch cycle controller coupled to receive the reference oscillating signal and coupled to provide a cycle control signal to the clock generator, the clock generator stretching a cycle of the clock signal responsive to a value of the cycle control signal to generate a clock signal stretch cycle;
- wherein
- the clock signal comprises a first clock signal and a second clock signal;
- the clock generator is coupled to provide the first clock signal and the second clock signal responsive to receiving the reference oscillating signal;
- the stretch cycle controller is coupled to receive a stretch signal and to provide the cycle control signal for stretching at least one cycle of at least one of the first and second clock signals responsive to a value of the stretch signal;
- the clock generator includes a state counter having a counter cycle, the counter cycle having a cycle time at least twice as long as a longest period of periods of the first and second clock signals;
- and
- the cycle control signal comprises at least three cycle control signals, the at least three cycle control signals including
- a first cycle control signal for stretching the at least one of the first and second clock signals during a first half of the counter cycle responsive to the stretch signal indicating a first half cycle stretch;
- a second cycle control signal for stretching the at least one of the first and second clock signals during a second half of the counter cycle responsive to the stretch signal indicating a second half cycle stretch;
- and
- a third cycle control signal for stretching the at least one of the first and second clock signals during the first half of the counter cycle and the second half of the counter cycle responsive to the stretch signal indicating a both-halves cycle stretch.
11 more elements
A clock generating circuit comprising:
- a clock generator coupled to receive a reference oscillating signal, the clock generator providing a clock signal responsive to the reference oscillating signal;
- a stretch cycle controller coupled to provide a cycle control signal to the clock generator, the clock generator stretching a cycle of the clock signal responsive to a value of the cycle control signal to generate a clock signal stretch cycle;
- and
- a phase locking circuit coupled to provide the reference oscillating signal to the clock generator and the stretch cycle controller, and coupled to receive the clock signal from the clock generator and a mask signal from the stretch cycle controller to mask the clock signal from the phase locking circuit during a stretch cycle.
1 more element
An apparatus for stretching clock signals in a computer system, the apparatus comprising:
- a stretch control circuit coupled to receive a reference clock signal and coupled to receive a debug signal, the stretch control circuit providing at least one control signal responsive to the debug signal;
- and
- a stretch functional circuit coupled to receive the at least one control signal from the stretch control circuit and coupled to receive the reference clock signal, the stretch functional circuit for providing a plurality of apparatus clock signals, the stretch functional circuit stretching a cycle of at least one of the apparatus clock signals responsive to the at least one control signal to generate a stretch cycle of the at least one of the apparatus clock signals;
- wherein the stretch functional circuit includes
- a state machine for providing state information, the state information identifying the state of the state machine;
- and
- a state decoder for receiving the state information from the state machine, the state decoder providing the apparatus clock signals, each apparatus clock signal being determined by at least a portion of the state information selected by the at least one control signal;
- and wherein
- the state information is represented as a plurality of state bits, each state bit being asserted when the state machine is in a corresponding state;
- and
- the state decoder comprises:
- a circuit for combining values of the state bits to generate a plurality of combined state signals, the plurality of combined signals including
- a first combined state signal providing a normal operation clock signal, and
- a second combined state signal providing a stretched clock signal;
- a selection circuit for selecting one of the first and second combined state signals to provide the at least one apparatus clock signal.
12 more elements
An apparatus for stretching clock signals in a computer system, the apparatus comprising:
- a stretch control circuit coupled to receive a debug signal and a reference clock signal, the stretch control circuit providing at least one control signal responsive to the debug signal;
- a stretch functional circuit coupled to receive the at least one control signal from the stretch control circuit and coupled to receive the reference clock signal, the stretch functional circuit for providing a plurality of apparatus clock signals, the stretch functional circuit stretching a cycle of at least one of the apparatus clock signals responsive to the at least one control signal to generate a stretch cycle of the at least one of the apparatus clock signals;
- and
- a phase locking circuit coupled to the stretch control circuit and the stretch functional circuit for providing the reference clock signal, the phase locking circuit including an output, the stretch control circuit providing a mask signal to the phase locking circuit to allow the output of the phase locking circuit to remain substantially unaffected by clock stretch when the mask signal has a first value.
1 more element
An apparatus for stretching clock signals, the apparatus comprising:
- means for providing a stretch control signal responsive to receiving a debug stretch cycle signal;
- means for providing a clock signal, the clock signal having a period, the means for providing the clock signal including means for stretching the period of the clock signal responsive to a first value of the stretch control signal to generate a stretch cycle of the clock signal;
- and
- a phase locked loop means coupled to receive the clock signal and to receive a mask signal from the means for providing the stretch control signal, the mask signal being for masking the clock signal, the phase locked loop means being coupled to provide an oscillating signal derived from the clock signal and the mask signal to the means for providing the stretch control signal and the means for providing the clock signal.
1 more element
An apparatus comprising:
- a counter coupled to receive an oscillating signal and coupled to provide a plurality of state lines for indicating the state of the counter;
- a stretch cycle controller coupled to receive the oscillating signal and coupled to provide a cycle control signal;
- and
- a state decoder coupled to receive the state lines and the cycle control signal and coupled to provide a clock signal, the state decoder including
- a combination circuit for combining sets of the state lines to generate a plurality of combined state signals, the plurality of combined state signals including
- a first combined state signal providing a normal operation clock signal, and
- a second combined state signal providing a stretched clock signal including a stretch cycle;
- and
- a selection circuit for selecting one of the first and second combined state signals to provide the clock signal.
6 more elements
A microprocessor comprising:
- a state machine coupled to receive an oscillating signal and coupled to provide a plurality of state lines for indicating the state of the state machine;
- a stretch cycle controller coupled to receive the oscillating signal and coupled to provide a cycle control signal;
- and
- a state decoder coupled to receive the state lines and the cycle control signal and coupled to provide a clock signal, the state decoder including
- a combination circuit for combining sets of the state lines to generate a plurality of combined state signals, the plurality of combined state signals including
- a first combined state signal providing a normal operation clock signal, and
- a second combined state signal providing a stretched clock signal including a stretch cycle;
- and
- a selection circuit for selecting one of the first and second combined state signals to provide the clock signal.
6 more elements
Dependencies are inferred from the claim text.