Fast start-up processor clock generation method and system

A system comprising:

• a Phase Locked Loop (PLL) generating a first signal and a PLL clock based on a reference clock, wherein:
• the PLL comprises a charge pump having a narrow bandwidth mode and a wide bandwidth mode,
• the first signal is generated based on the PLL achieving an expected frequency within a predefined bandwidth, and
• the expected frequency is a specified multiple of the reference clock;
• a divider circuit receiving the PLL clock and a select signal and generating a system clock, wherein:
• the divider circuit generates the system clock at a first frequency if the select signal is in a first state and generates the system clock at a second frequency if the select signal is in a second state;
• a enable circuit receiving the first signal and generating a second signal wherein the enable circuit comprises a counter;
• a processor receiving the first signal and selectively generating a third signal;
• and
• a select circuit receiving the second signal and the third signal and generating the select signal in response to the second signal and the third signal.

A method of operation for a data processing system, the method comprising:

• A) generating a system clock from a PLL clock by providing one of a plurality of frequencies based on receipt of a select signal;
• B) generating the select signal based on receipt of a second signal and a third signal;
• C) generating the second signal after receiving a first signal;
• D) generating the third signal in a processor that is enabled by the first signal;
• and
• E) generating the first signal in response to frequency locking the PLL clock.