Sample and hold circuit having a waveform shaping circuit

A sample and hold circuit comprising:

• a hold capacitor,
• an analog switch with an n-channel MOSFET and a p-channel MOSFET connected parallel to each other and connected to said hold capacitor, with the gates of said n-channel and said p-channel MOSFETs providing inputs to said analog switch,
• a waveform shaping circuit comprising:
• an XSEL signal and a SEL signal input, with the XSEL signal in a stable state in either a first logic level or a second logic level, with the second logic level opposite the first logic level, the logic level of said SEL signal is output as an OUT signal, the logic level of said XSEL signal is output as an XOUT signal, where said OUT signal and said XOUT signal are connected to the inputs of said analog switch;
• wherein in the transient state in which said XSEL signal starts logic inversion from the first logic level to the second logic level, and then said SEL signal starts logic inversion from the second logic level to the first logic level,
• upon detection of the start of logic inversion of said XSEL signal, a change is started for the logic level of said OUT signal and the logic level of said XOUT signal;
• then, upon detection of the start of logic inversion of said SEL signal, the logic level of said OUT signal and the logic level of said XOUT signal are further changed, and logic inversion of said OUT signal and logic inversion of said XOUT signal are completed, and
• wherein said SEL signal is formed when said XSEL signal is inverted by an inverter;
• and said analog switch has a constitution such that it is set to the conductive state and cutoff state corresponding to the logic level of said XOUT signal and the logic level of said OUT signal state;
• and said hold capacitor has a constitution such that when said analog switch is conductive, charging/discharge takes place at the voltage to be sampled;
• and, when said analog switch is in the cutoff state, the voltage is maintained.