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US 5,963,061 AGranted
Switch for minimizing transistor exposure to high voltage
AssigneeMicron Technology, Inc.
InventorMichael S. Briner
Life of this patent
Estimating the term…
Abstract
An asymmetric switch which minimizes transistor exposure to high voltage includes one pair of P-channel transistors with both N-wells coupled back to the programming voltage source and one pair of P-channel transistors with independent N-wells. Two pairs of N-channel transistors and an inverting circuit are also included to provide complementary input voltages to the switch. The P-channel and N-channel transistors used as guard devices may be biased by the same voltage or separate voltages.
Claims18
An asymmetric switch comprising:
- a first p-channel transistor having a source, drain, and gate, the first p-channel transistor is formed in a well, the source and well are coupled to a high voltage Vpp;
- a second p-channel transistor having a source, drain, and gate, the second p-channel transistor is formed in a well, the second p-channel well is coupled to Vpp, the second p-channel source is connected to the drain of the first p-channel transistor, the second p-channel drain is connected to a first output connection, and the second p-channel gate is connected to a supply voltage Vcc which has a potential less than Vpp;
- a first pulldown circuit is connected to the drain of the second p-channel transistor, the first pull-down circuit comprises series connected n-channel transistors which couple the drain of the second p-channel transistor to ground potential in response to a low input signal;
- a third p-channel transistor having a source, drain, and gate, the third p-channel transistor is formed in a well, the source and well are coupled to Vpp, and the gate of the third p-channel transistor is connected to the first output connection, the drain of the third p-channel transistor is connected to the gate of the first p-channel transistor;
- a fourth p-channel transistor having a source, drain, and gate, the fourth p-channel transistor is formed in a well, the fourth p-channel well and source are connected to the drain of the third p-channel transistor, the fourth p-channel drain is connected to a second output connection, and the fourth p-channel gate is connected to Vcc;
- and
- a second pulldown circuit is connected to the drain of the fourth p-channel transistor, the second pull-down circuit comprises series connected n-channel transistors which couple the drain of the fourth p-channel transistor to ground potential in response to a high input signal.
4 more elements
An asymmetric switch comprising:
- a first p-channel transistor having a source, drain, and gate, the first p-channel transistor is formed in a well, the source and well are coupled to a high voltage Vpp;
- a second p-channel transistor having a source, drain, and gate, the second p-channel transistor is formed in a well, the second p-channel well and source are connected to the drain of the first p-channel transistor, the second p-channel drain is connected to a first output connection, and the second p-channel gate is connected to a supply voltage Vcc which has a potential less than Vpp;
- a first pulldown circuit is connected to the drain of the second p-channel transistor, the first pull-down circuit comprises series connected n-channel transistors which couple the drain of the second p-channel transistor to ground potential in response to a low input signal;
- a third p-channel transistor having a source, drain, and gate, the third p-channel transistor is formed in a well, the source and well are coupled to Vpp, and the gate of the third p-channel transistor is connected to the drain of the first p-channel transistor;
- a fourth p-channel transistor having a source, drain, and gate, the fourth p-channel transistor is formed in a well, the fourth p-channel well is connected to Vpp, the fourth p-channel source is connected to the drain of the third p-channel transistor, the fourth p-channel drain is connected to both a second output connection and the gate of the first p-channel transistor, and the fourth p-channel gate is connected to Vcc;
- and
- a second pulldown circuit is connected to the drain of the fourth p-channel transistor, the second pull-down circuit comprises series connected n-channel transistors which couple the drain of the fourth p-channel transistor to ground potential in response to a high input signal.
4 more elements
An asymmetric switch comprising:
- a first p-channel transistor having a source, drain, and gate, the first p-channel transistor is formed in a well, the source and well are coupled to a high voltage Vpp;
- a second p-channel transistor having a source, drain, and gate, the second p-channel transistor is formed in a well, the second p-channel well is coupled to Vpp, the second p-channel source is connected to the drain of the first p-channel transistor, the second p-channel drain is connected to a first output connection, and the second p-channel gate is connected to a p-channel transistor bias voltage Vpt which has a potential less than Vpp;
- a first pulldown circuit is connected to the drain of the second p-channel transistor, the first pull-down circuit comprises series connected n-channel transistors which couple the drain of the second p-channel transistor to ground potential in response to a low input signal;
- a third p-channel transistor having a source, drain, and gate, the third p-channel transistor is formed in a well, the source and well are coupled to Vpp, and the gate of the third p-channel transistor is connected to the first output connection, the drain of the third p-channel transistor is connected to the gate of the first p-channel transistor;
- a fourth p-channel transistor having a source, drain, and gate, the fourth p-channel transistor is formed in a well, the fourth p-channel well and source are connected to the drain of the third p-channel transistor, the fourth p-channel drain is connected to a second output connection, and the fourth p-channel gate is connected to Vpt;
- and
- a second pulldown circuit is connected to the drain of the fourth p-channel transistor, the second pull-down circuit comprises series connected n-channel transistors which couple the drain of the fourth p-channel transistor to ground potential in response to a high input signal.
4 more elements
A computer system comprising:
- a processor;
- a clock circuit connected to the processor;
- a module, connected to the processor, for interfacing the processor with peripheral devices;
- and
- a memory module connected to the processor, the memory module including a switch for use in programming the memory module, the switch comprises:
- a first p-channel transistor having a source, drain, and gate, the first p-channel transistor is formed in a well, the source and well are coupled to a high voltage Vpp;
- a second p-channel transistor having a source, drain, and gate, the second p-channel transistor is formed in a well, the second p-channel well is coupled to Vpp, the second p-channel source is connected to the drain of the first p-channel transistor, the second p-channel drain is connected to a first output connection, and the second p-channel gate is connected to a supply voltage Vcc which has a potential less than Vpp;
- a first pulldown circuit is connected to the drain of the second p-channel transistor, the first pull-down circuit comprises series connected n-channel transistors which couple the drain of the second p-channel transistor to ground potential in response to a low input signal;
- a third p-channel transistor having a source, drain, and gate, the third p-channel transistor is formed in a well, the source and well are coupled to Vpp, and the gate of the third p-channel transistor is connected to the first output connection, drain of the third p-channel transistor is connected to the gate of the first p-channel transistor;
- a fourth p-channel transistor having a source, drain, and gate, the fourth p-channel transistor is formed in a well, the fourth p-channel well and source are connected to the drain of the third p-channel transistor, the fourth p-channel drain is connected a second output connection, and the fourth p-channel gate is connected to Vcc;
- and
- a second pulldown circuit is connected to the drain of the fourth p-channel transistor, the second pull-down circuit comprises series connected n-channel transistors which couple the drain of the fourth p-channel transistor to ground potential in response to a high input signal.
9 more elements
A computer system comprising:
- a processor;
- a clock circuit connected to the processor;
- a module, connected to the processor, for interfacing the processor with peripheral devices;
- and
- a memory module connected to the processor, the memory module including a switch for use in programming the memory module, the switch comprises:
- a first p-channel transistor having a source, drain, and gate, the first p-channel transistor is formed in a well, the source and well are coupled to a high voltage Vpp;
- a second p-channel transistor having a source, drain, and gate, the second p-channel transistor is formed in a well, the second p-channel well and source are connected to the drain of the first p-channel transistor, the second p-channel drain is connected to a first output connection, and the second p-channel gate is connected to a supply voltage Vcc which has a potential less than Vpp;
- a first pulldown circuit is connected to the drain of the second p-channel transistor, the first pull-down circuit comprises series connected n-channel transistors which couple the drain of the second p-channel transistor to ground potential in response to a low input signal;
- a third p-channel transistor having a source, drain, and gate, the third p-channel transistor is formed in a well, the source and well are coupled to Vpp, and the gate of the third p-channel transistor is connected to the drain of the first p-channel transistor;
- a fourth p-channel transistor having a source, drain, and gate, the fourth p-channel transistor is formed in a well, the fourth p-channel well is connected to Vpp, the fourth p-channel source is connected to the drain of the third p-channel transistor, the fourth p-channel drain is connected to both a second output connection and the gate of the first p-channel transistor, and the fourth p-channel gate is connected to Vcc;
- and
- a second pulldown circuit is connected to the drain of the fourth p-channel transistor, the second pull-down circuit comprises series connected n-channel transistors which couple the drain of the fourth p-channel transistor to ground potential in response to a high input signal.
9 more elements
A computer system comprising:
- a processor;
- a clock circuit connected to the processor;
- a module, connected to the processor, for interfacing the processor with peripheral devices;
- and
- a memory module connected to the processor, the memory module including a switch for use in programming the memory module, the switch comprises:
- a first p-channel transistor having a source, drain, and gate, the first p-channel transistor is formed in a well, the source and well are coupled to a high voltage Vpp;
- a second p-channel transistor having a source, drain, and gate, the second p-channel transistor is formed in a well, the second p-channel well is coupled to Vpp, the second p-channel source is connected to the drain of the first p-channel transistor, the second p-channel drain is connected to a first output connection, and the second p-channel gate is connected to a p-channel transistor bias voltage Vpt which has a potential less than Vpp;
- a first pulldown circuit is connected to the drain of the second p-channel transistor, the first pull-down circuit comprises series connected n-channel transistors which couple the drain of the second p-channel transistor to ground potential in response to a low input signal;
- a third p-channel transistor having a source, drain, and gate, the third p-channel transistor is formed in a well, the source and well are coupled to Vpp, and the gate of the third p-channel transistor is connected to the first output connection, the drain of the third p-channel transistor is connected to the gate of the first p-channel transistor;
- a fourth p-channel transistor having a source, drain, and gate, the fourth p-channel transistor is formed in a well, the fourth p-channel well and source are connected to the drain of the third p-channel transistor, the fourth p-channel drain is connected to a second output connection, and the fourth p-channel gate is connected to Vpt;
- and
- a second pulldown circuit is connected to the drain of the fourth p-channel transistor, the second pull-down circuit comprises series connected n-channel transistors which couple the drain of the fourth p-channel transistor to ground potential in response to a high input signal.
9 more elements
Dependencies are inferred from the claim text.