Phase frequency detector having reduced blind spot

A method for performing phase error detection over an extended phase error range, wherein the method comprises:

• detecting a first positive transition in a first clock signal and providing a first sustained indication of the first positive transition;
• setting a first latch in response to the first sustained indication;
• asserting a first output while the first latch is set;
• detecting a second positive transition in a second clock signal and providing a second sustained indication of the second positive transition;
• setting a second latch in response to the second sustained indication;
• asserting a second output while the second latch is set;
• and
• resetting the first and second latches in response to both the first and second latches being set, wherein the resetting is performed by a reset controller, and wherein the first and second latches are respectively coupled to first and second pulse generators via the reset controller, wherein the reset controller isolates the first and second latches from the first and second pulse generators during the resetting.

A phase-frequency detector which comprises:

• a first latch configured to hold a first state when reset and a second state when set;
• a second latch configured to hold the first state when reset and the second state when set;
• a reset controller coupled to the first and second latches and configured to reset the first and second latches when both the first and second latches are set;
• a first edge-triggered pulse generator coupled to the first latch and configured to set the first latch in response to a transition in a first clock signal;
• and
• a second edge-triggered pulse generator coupled to the second latch and configured to set the second latch in response to a transition in a second clock signal;
• wherein the first and second edge-triggered pulse generators respectively set the first and second latches by providing a logic value for an interval having a pulse duration T.sub.PULSE ;
• and
• wherein the first and second edge-triggered pulse generators have a propagation delay T.sub.CLK.fwdarw.Q, wherein the reset controller has a detection path delay T.sub.Q.fwdarw.R and an assertion path delay T.sub.R.fwdarw.Q, and wherein the pulse duration T.sub.PULSE is substantially equal to T.sub.CLK.fwdarw.Q +2T.sub.Q.fwdarw.R +T.sub.R.fwdarw.Q.

A phase-frequency detector which comprises:

• a first latch configured to hold a first state when reset and a second state when set;
• a second latch configured to hold the first state when reset and the second state when set;
• a reset controller coupled to the first and second latches and configured to reset the first and second latches when both the first and second latches are set;
• a first edge-triggered pulse generator coupled to the first latch and configured to set the first latch in response to a transition in a first clock signal;
• and
• a second edge-triggered pulse generator coupled to the second latch and configured to set the second latch in response to a transition in a second clock signal;
• wherein the first and second edge-triggered pulse generators respectively set the first and second latches by providing a logic value for an interval having a pulse duration T.sub.PULSE ;
• and
• wherein the first and second edge-triggered pulse generators have a propagation delay T.sub.CLK.fwdarw.Q, wherein the reset controller has a detection path delay T.sub.Q.fwdarw.R and an assertion path delay T.sub.R.fwdarw.Q, and wherein the difference between pulse duration T.sub.PULSE and T.sub.CLK.fwdarw.Q +2T.sub.Q.fwdarw.R +T.sub.R.fwdarw.Q is less than 10% of a clock cycle of the second clock signal.

A phase-frequency detector which comprises:

• a first latch configured to hold a first state when reset and a second state when set;
• a second latch configured to hold the first state when reset and the second state when set;
• a reset controller coupled to the first and second latches and configured to reset the first and second latches when both the first and second latches are set;
• a first edge-triggered pulse generator coupled to the first latch and configured to set the first latch in response to a transition in a first clock signal;
• and
• a second edge-triggered pulse generator coupled to the second latch and configured to set the second latch in response to a transition in a second clock signal;
• wherein the reset controller includes:
• a first isolation transistor coupled between the first latch and the first pulse generator, wherein the first isolation transistor is configured to isolate the first latch from the first pulse generator when a reset signal is asserted;
• a first reset transistor coupled between a first logic value and the first latch, wherein the first reset transistor is configured to reset the first latch when the reset signal is asserted;
• a second isolation transistor coupled between the second latch and the second pulse generator, wherein the second isolation transistor is configured to isolate the second latch from the second pulse generator when the reset signal is asserted;
• and
• a second reset transistor coupled between the first logic value and the second latch, wherein the second reset transistor is configured to reset the second latch when the reset signal is asserted.

A phase-frequency detector which comprises:

• a first latch configured to hold a first state when reset and a second state when set;
• a second latch configured to hold the first state when reset and the second state when set;
• a reset controller coupled to the first and second latches and configured to reset the first and second latches when both the first and second latches are set;
• a first edge-triggered pulse generator coupled to the first latch and configured to set the first latch in response to a transition in a first clock signal;
• and
• a second edge-triggered pulse generator coupled to the second latch and configured to set the second latch in response to a transition in a second clock signal;
• wherein the first edge-triggered pulse generator comprises:
• a start transistor coupled to receive the first clock signal and configured to be conductive when the first clock signal is asserted;
• a time-delay inverter configured with a predetermined propagation delay T.sub.PULSE, wherein the time-delay inverter is coupled to receive and invert the first clock signal;
• and
• a stop transistor coupled in series with the start transistor, coupled to receive an output signal from the time-delay inverter, and configured to be conductive when the output signal is asserted.