Phase frequency detector

An integrated circuit comprising:

• two phase frequency detector (PFD) half-cells coupled together;
• each of said half-cells including a pulse generator including an input port and an output port, and a stage coupled between two different voltage levels, said stage including multiple input ports and an output port;
• the output port of said pulse generator being coupled to a first of said multiple input ports of said stage to set the output port of said stage in response, at least in part, to said input port of said pulse generator receiving a clock pulse;
• a second of said multiple input ports of said stage being coupled to the output port of the stage of the other half-cell to inhibit the setting of the output port of said stage when the clock pulse received by the input port of said pulse generator is sufficiently delayed relative to the clock pulse received by the input port of the pulse generator of the other half-cell;
• the output port of the pulse generator of the other half-cell being coupled through a time delay to a third of said multiple input ports of said stage to reset the output port of said stage.

A method of producing an up signal pulse and a down signal pulse for a phase-locked loop (PLL), said method comprising:

• receiving a reference clock signal pulse and a PLL feedback clock signal pulse, a phase delay separating the clock signal pulses;
• producing the up signal pulse and the down signal pulse in response to the two received clock signal pulses, the up signal pulse and the down signal pulse overlapping for a period of time when the magnitude of the phase delay is less than a particular value;
• and
• producing either only an up signal pulse or only a down signal pulse in response to the two received clock signal pulses otherwise.