Chip level bias for buffers driving voltages greater than transistor tolerance
AssigneeLSI Logic Corporation
InventorsJonathan Schmitt, Paul Torgerson
Life of this patent
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Abstract
An integrated circuit includes a core region and an input-output (I/O) region which has an I/O slot and a voltage supply slot. First and second voltage supply buses and a bias voltage bus extend along the I/O region through the I/O slot and the voltage supply slot. A bias voltage generator is fabricated in the voltage supply slot and is electrically coupled between the first and second voltage supply buses. The bias voltage generator has a bias voltage output which is electrically coupled to the bias voltage bus. A buffer is fabricated in the I/O slot for interfacing with the core region. The buffer includes a bias voltage input which is electrically coupled to the bias voltage bus.
Claims19
An integrated circuit comprising:
- a core region;
- an input-output (I/O) region comprising an I/O slot and a voltage supply slot;
- first and second voltage supply buses and a bias voltage bus which extend along the I/O region through the I/O slot and the voltage supply slot;
- a bias voltage generator fabricated in the voltage supply slot and electrically coupled between the first and second voltage supply buses and comprising a bias voltage output electrically coupled to the bias voltage bus;
- and
- a buffer fabricated in the I/O slot and interfacing with the core region, the buffer comprising a bias voltage input electrically coupled to the bias voltage bus.
An integrated circuit comprising:
- a core region;
- an input-output (I/O) region comprising an I/O slot and a voltage supply slot;
- first and second I/O voltage supply buses, first and second core supply buses and a bias voltage bus which extend along the I/O region through the I/O slot and the voltage supply slot;
- a bias voltage generator fabricated in the voltage supply slot and electrically comprising a bias voltage output electrically coupled to the bias voltage bus;
- a buffer fabricated in the I/O slot and comprising:
- a core terminal and a pad terminal;
- a pull-up transistor coupled between the first I/O voltage supply bus and the pad terminal and having a pull-up control terminal;
- a pull-up voltage protection transistor coupled between the pull-up transistor and the pad terminal and having a control terminal coupled to the bias voltage bus;
- a pull-up control circuit coupled between the core terminal and the pull-up control terminal;
- a pull-down transistor coupled between the second I/O voltage supply bus and the pad terminal and having a pull-up control terminal;
- and
- a pull-down control circuit coupled between the core terminal and the pull-down control terminal.
Dependencies are inferred from the claim text.