Full and empty flag generator for synchronous FIFOs

An apparatus comprising:

• a first state machine having a first input receiving a write clock, a second input receiving a first read clock and a third input receiving a look-ahead signal, said first state machine manipulating said inputs to produce a first output signal that is either at a first logic state or at a second logic state;
• a second state machine having a first input receiving said write clock, a second input receiving a second read clock, a third input receiving a non look-ahead signal and a fourth input for receiving control information, said second state machine manipulating said inputs to produce a second output signal that is either at a first logic state or at a second logic state;
• a latch having a first input receiving said first output signal, a second input receiving said second output signal, a third output signal equal to said first output signal and a fourth output signal equal to said second output signal, said latch for holding said third and fourth output signals until said first and second output signals change logic states, said fourth output signal representing an output flag that is at one logic state when said FIFO is empty and is at another logic state when said PIFO is not empty;
• and
• logic means having a logic input receiving said third output signal of said latch and an output presenting said fourth input to said second state machine, said logic means uses said logic input to produce said control information.

An apparatus comprising:

• delay means having an input receiving a write clock and a delay output, said delay means provides a predetermined delay to said delay output;
• a first state machine having a first input receiving said delay output, a second input receiving a first read clock and a third input receiving a look-ahead signal, said first state machine manipulating said inputs to produce a first output that is either at a first logic state or at a second logic state;
• a second state machine having a first input receiving said write clock, a second input receiving a second read clock, a third input receiving a non look-ahead signal and a fourth input for receiving control information, said state machine manipulating said inputs to produce a second output that is either at a first logic state or at a second logic state;
• a latch having a first input receiving said first output, a second input receiving said second output, a third output signal equal to said first output and a fourth output signal equal to said second output, said latch for holding said second and third output signals until said first and second outputs change states, said third output signal representing an output flag that is at one logic state when said FIFO is empty and is at another logic state when said FIFO is not empty;
• and
• logic means having an input receiving said fourth output signal of said latch and an output presenting said fourth input of said second state machine, said logic means uses said input to produce said control information.

An apparatus comprising:

• a first state machine receiving a write clock, a first read clock and a look-ahead signal, said first state machine manipulating said write clock, said first read clock and said look-ahead signal to produce a first output signal that is either at a first logic state or at a second logic state;
• a second state machine receiving said write clock, a second read clock, a non look-ahead signal and control information, said second state machine manipulating said write clock, said read clock, said non look-ahead signal and said control signal to produce a second output signal that is either at a first logic state or at a second logic state;
• a latch receiving said first output signal, said second output signal, a third output signal and a fourth output signal, said latch configured to hold said third and fourth output signals until said first and second output signals change logic states, said fourth output signal representing an output flag that is at one logic state when said FIFO is at a full or empty boundary and is at another logic state when said FIFO is not at said boundary;
• and
• logic means receiving said third output signal of said latch and presenting said control information in response to said third output signal.

An apparatus comprising:

• a first state machine configured to generate a first output in response to (i) a write clock, (ii) a first read clock and (iii) a look-ahead signal;
• a second state machine configured to generate a second output signal in response to (i) said write clock, (ii) a second read clock, (iii) a non look-ahead signal and (iv) a control signal;
• a latch configured to:
• (a) receive (i) said first output signal and (ii) said second output signal,
• (b) present (i) a third output signal and (ii) a fourth output signal, and
• (c) hold said third and fourth output signals until said first and second output signals change logic states, wherein said fourth output signal represents an output flag that is at one logic state when said FIFO is at a full or empty boundary and is at another logic state when said FIFO is not at said boundary;
• and
• a logic circuit configured to present said control signal to said second state machine in response to said third output signal.