Interface circuit between different potential levels

An interface circuit for providing a low-voltage output signal, connected to an external circuit that operates on a high supply voltage, the interface circuit having a pull-up p-channel MOS transistor formed between and connected to an output pad and a low-voltage power source, the output Pad being connected to the external circuit, the pull-up transistor being turned on and off in response to an input voltage applied to a gate electrode of the pull-up transistor and providing the low-voltage signal according to a low supply voltage provided by the low-voltage power source, the interface circuit further comprising:

• an output potential transfer circuit for providing a first signal if a voltage at the output pad is higher than a reference level, comprising:
• a p-channel MOS transistor having a first main electrode connected to said output pad, a second main electrode, and a gate electrode to receive a voltage of "Vcc-Vth", where Vcc is the low supply voltage provided by the low-voltage power source and Vth is a gate threshold voltage;
• and
• a resistor formed between and connected to the second main electrode of the p-channel MOS transistor and a ground;
• a reverse current prevention p-channel MOS transistor formed between and connected to the pull-up transistor and the output pad to be turned on and off according to the first signal;
• a switched floating n-well circuit for biasing a substrate of the reverse current prevention transistor to the low supply voltage if the voltage at the output pad is below a predetermined voltage, and to a floating state if the voltage at the output pad is above the predetermined voltage;
• and
• a prebuffer connected to the gate electrode of said pull-up transistor.

An interface circuit for providing a low-voltage output signal, connected to an external circuit that operates on a high supply voltage, the interface circuit having a pull-up p-channel MOS transistor formed between and connected to an output pad and a low-voltage power source, the output pad being connected to the external circuit, the pull-up transfer being turned on and off in response to an input voltage applied to a gate electrode of the pull-up transistor and providing the low-voltage signal according to a low supply voltage provided by the low-voltage power source, the interface circuit further comprising:

• an output potential transfer circuit for providing a first signal if a voltage at the output pad is higher than a reference level;
• a reverse current prevention p-channel MOS transistor formed between and connected to the pull-up transistor and the output pad, to be turned on and off according to the first signal;
• a switched floating n-well circuit for biasing a substrate of the reverse current prevention transistor to the low supply voltage if the voltage at the output pad is below a predetermined value, and to a floating state if the voltage at the output pad is above the predetermined voltage, comprising a p-channel MOS transistor having a first main electrode connected to the low-voltage power source and a second main electrode and substrate both connected to a substrate of the reverse current prevention p-channel MOS transistor and to a substrate of said p-channel MOS transistor of the output potential transfer circuit;
• and a prebuffer connected to the gate electrode of said pull-up transistor.

A computer system comprising:

• (a) a CPU;
• (b) a memory operating on a high supply voltage provided by a high-voltage power source;
• (c) a high-voltage bus connected to the memory;
• (d) a control LSI connected to the CPU and high-voltage bus and operating on a low supply voltage provided by a low-voltage power source, the control LSI having an interface circuit comprising:
• an output pad connected to the high-voltage bus;
• a potential transfer circuit connected to the output pad;
• a prebuffer;
• a first p-channel MOS transistor having a first main electrode, a second main electrode connected to the low-voltage power source, and a gate electrode connected to an output of the prebuffer;
• a second p-channel MOS transistor having a first main electrode connected to the output pad, a second main electrode connected to the first main electrode of the first p-channel MOS transistor, and a gate electrode only connected to the potential transfer circuit;
• and
• a switched floating n-well circuit formed between and connected to the low-voltage power source and the output pad, to control a substrate voltage of the first and second p-channel MOS transistors;
• and
• (e) peripheral equipments connected to the control LSI.