Semiconductor integrated circuit device
AssigneeMitsubishi Denki Kabushiki Kaisha
InventorsYasunori Shingaki, Nobusuke Abe
Life of this patent
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Abstract
A semiconductor integrated circuit device incorporates logical arithmetic circuits (11) in order to set the internal circuits (7, 10) to a stable state. Each logical arithmetic circuit (11) is placed between each of input terminals (5, 9) that are not used during a boot operation mode, and each of internal circuits (7, 10).
Claims20
A semiconductor integrated circuit device fabricated by a Complementary Metal Oxide Silicon fabrication process (CMOS fabrication process), comprising:
- a first memory circuit;
- and
- logical arithmetic circuits, each placed on a signal line through which each of internal circuits is connected to each of input terminals that being not used during a boot operation mode in which data items being written into said first memory circuit, for performing a logical operation between input signal inputted through said input terminals and a signal that becomes a fixed signal level during said boot operation mode, and for outputting an operation result to said internal devices.
A semiconductor integrated circuit device fabricated by a Complementary Metal Oxide Silicon fabrication process (CMOS fabrication process), comprising:
- a first memory circuit;
- a second memory circuit for inputting a reset signal and a start signal, and for storing an output state of said own second memory circuit that has been set by receiving said reset signal until receiving of a following start signal;
- and
- logical arithmetic circuits, each placed on a signal line through which each of internal circuits is connected to each of input terminals that being not used during a boot operation mode in which data items being written into said first memory circuit, for performing a logical operation between input signal inputted through said input terminals and an output signal transferred from said second memory circuit, and for outputting an operation result to said internal devices.
A semiconductor integrated circuit device fabricated by a Complementary Metal Oxide Silicon fabrication process (CMOS fabrication process), comprising:
- a first memory circuit;
- a third memory circuit for inputting a reset signal and a start signal, and for storing an output state of said own third memory circuit that has been set by receiving said reset signal until receiving of a following start signal;
- and
- a judgement circuit for inputting an output signal from said third memory circuit and a mode signal to switch operation modes of said semiconductor integrated circuit device, and for outputting a judgement signal whose level during a state immediately following a reset state and during a boot operation mode in which data items being written into said first memory has a different level from a level in other states;
- and
- logical arithmetic circuits, each placed on a signal line through which each of internal circuits is connected to each of input terminals that being not used during said boot operation mode, for performing logical operation between input signal inputted through said input terminals and said judgement signal, and for outputting an operation result to said internal devices.
Dependencies are inferred from the claim text.