Programmable logic array integrated circuit architectures

A programmable logic array integrated circuit device comprising:

• a plurality of regions of programmable logic disposed on said device in a two-dimensional array of intersecting rows and columns of said regions, each of said regions being programmable to produce a region output signal which is any of a plurality of logic functions of a plurality of region input signals that are applied to that region;
• a plurality of regions of programmable memory usable by a user of the device to store and subsequently output data, said regions of programmable memory being disposed on said device in an additional column with one of said programmable memory regions being included in each of said rows;
• a plurality of first conductors associated with each of said rows and extending adjacent to and along the regions in the associated row for conveying signals between the regions in that row;
• a plurality of column conductors associated with each of said columns and extending adjacent to and along the regions in the associated column for conveying signals between the rows;
• first programmable logic connector circuitry associated with each of said regions of programmable logic for selectively connecting selected ones of the conductors that are adjacent to that region to inputs of that region in order to provide the region input signals for that region;
• second programmable logic connector circuitry associated with each of said regions of programmable logic for selectively connecting the region output signal of that region to a selected one of the conductors that are adjacent to that region;
• third programmable logic connector circuitry for selectively applying signals on selected ones of the first conductors associated with each of said rows to selected ones of the column conductors associated with each of said columns;
• and
• fourth programmable logic connector circuitry for selectively applying signals on selected ones of the column conductors associated with each of said columns to selected ones of the first conductors associated with each of said rows.

A programmable logic array integrated circuit device comprising:

• a plurality of regions of programmable logic, each of said regions being programmable to produce a region output signal which is any of a plurality of logic functions of a plurality of region input signals applied to that region, said regions being grouped in a plurality of subpluralities of adjacent ones of said regions such that each region is included in a plurality of different but partly overlapping ones of said subpluralities;
• an interconnection conductor associated with each of said subpluralities and extending adjacent to only the regions in the associated subplurality;
• and
• a plurality of region feeding conductors associated with each of said regions and being programmably connectable via programmable logic connectors to the interconnection conductors that are adjacent to the associated region for supplying said region input signals to that region from those interconnection conductors, said programmable logic connectors being bi-directional so that said region feeding conductors can also be used to make connections between interconnection conductors that are adjacent to the region with which said region feeding conductors are associated.

A programmable logic array integrated circuit device comprising:

• a plurality of regions of programmable logic disposed on said device in a two-dimensional array of intersecting rows and columns of said regions, each of said regions including a plurality of subregions of programmable logic, each of said subregions being programmable to produce a subregion output signal which is any of a plurality of logic functions of a plurality of subregion input signals that are applied to that subregion;
• a plurality of first conductors associated with each of said rows and extending adjacent to and along the regions in the associated row for conveying signals between the regions in that row;
• a plurality of column conductors associated with each of said columns and extending adjacent to and along the regions in the associated column for conveying signals between the rows, each of said column conductors associated with each of said columns being directly connected to a respective associated one and only one of the subregion output signals of the regions in that column;
• and
• a plurality of third conductors associated with each of said regions, said third conductors being programmably connectable between selected ones of the conductors that are adjacent to that region and inputs for the subregion input signals of that region.