Method and apparatus for characterized parasitic capacitance between integrated-circuit interconnects
AssigneeInternational Business Machines Corporation
InventorSani Richard Nassif
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Abstract
A method and apparatus for characterizing dimensions and parasitic capacitance between integrated-circuit interconnects are disclosed. The apparatus is a test structure including at least two substantially identical oscillators, at least two substantially identical counters, and a pulse generator. Each of the oscillators is connected to an integrated-circuit interconnect. Each of the counters is coupled to a respective oscillator. The pulse generator is utilized to inject a series of fixed-length clock pulses to each of the oscillators such that the parasitic capacitance of the integrated-circuit interconnects can be characterized by the ratio of oscillation periods of the oscillators to parasitic capacitances of the integrated-circuits.
Claims11
A test structure for characterizing relative parasitic capacitances of a plurality of integrated-circuit interconnects, wherein said test structure is embedded within an integrated-circuit, said test structure comprising:
- at least one oscillator connected to a plurality of integrated-circuit interconnects;
- and
- a counting mechanism, coupled to said at least one oscillator and to said plurality of integrated-circuit interconnects, that detects a ratio of oscillations on said plurality of integrated-circuit interconnects induced by said at least one oscillator such that relative parasitic capacitances of said plurality of integrated-circuit interconnects is determined.
A method for characterizing relative parasitic capacitances of a plurality of integrated-circuit interconnects, wherein said test structure is embedded within an integrated-circuit, said method comprising the steps of:
- connecting at least one oscillator to a plurality of integrated-circuit interconnects to be characterized;
- and
- detecting a ratio of oscillations on said plurality of integrated-circuit interconnects induced by said at least one oscillator such that relative parasitic capacitances of said plurality of integrated-circuit interconnects is determined.
Dependencies are inferred from the claim text.