Power surge management for high performance integrated circuit

A method for reducing disturbances in a power supply voltage delivered to a microprocessor integrated circuit chip by a power distribution system exhibiting increased AC impedance at mid-frequencies less than a nominal operating frequency of said microprocessor, said method comprising:

• sensing said power supply voltage delivered to said microprocessor;
• and
• regulating said power supply voltage on chip to within a power supply voltage level envelope within which devices and circuits of said microprocessor are reliably operable by performing a control action to reduce mid-frequency components of current supplied by said power distribution system.

An integrated circuit chip comprising:

• first circuitry defined thereon and operable to exhibit variations in current demand in response to temporal variations in an operating characteristic thereof, said circuitry couplable to define, in conjunction with components external to said integrated circuit chip, a power distribution system exhibiting AC impedance characteristics having a mid-frequency resonance, wherein said first circuitry is nominally operable at a high-frequency greater than said mid-frequency, and wherein said mid-frequency resonance is excitable by said variations in current demand to cause disturbances in power supply voltage delivered on-chip;
• a feedback control circuit defined on said integrated circuit chip and responsive to said disturbances in power supply voltage to control overall current demand of said integrated circuit chip and thereby regulate said disturbances to within a design tolerance of said integrated circuit chip.