Semiconductor device having simple protective structure and process of fabrication thereof
AssigneeNEC Corporation
InventorNaoto Kimura
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AssigneeNEC Corporation
InventorNaoto Kimura
Estimating the term…
A semiconductor integrated circuit device has a protective structure between a semiconductor chip and a ball grid array, and the protective structure has a thin polyimide film bonded to the surface of the semiconductor chip and a thick stress relaxation layer covering conductive strips connected between pads on the surface and the ball grid array; when thermal stress is exerted on the ball grid array, the thick stress relaxation layer allows said ball grid array to move so as to take up the thermal stress.
A semiconductor device comprising:
A semiconductor device comprising:
Dependencies are inferred from the claim text.
No related US applications are recorded in the indexed filing history.
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Interconnections or connectors in packages: bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
Interconnections or connectors in packages: bond pads, in general
Manufacture or treatment: of insulating or insulated package substrates, or of interposers, or of redistribution layers
Package substrates; Interposers; Redistribution layers [RDL]: insulating or insulated package substrates; Interposers; Redistribution layers
Term ended 13 Oct 2018 (estimated)
USPTO file history isn’t available for this patent, so only indexed dates are shown.
This invention relates to a semiconductor device and, more particularly, to a semiconductor device having a protective structure between a ball grid array and a semiconductor chip and a process of fabrication thereof.
A semiconductor integrated circuit device is, by way of example, mounted on an insulating substrate. The integrated circuit is electrically connected to a conductive pattern on the rigid substrate, and the following interconnection is used between the integrated circuit and the conductive pattern.
FIG. 1 illustrates the prior art interconnection. Reference numeral 1 designates a semiconductor chip, and various circuit components (not shown) are integrated on the semiconductor chip. The circuit components are connected through internal signal lines (not shown), and form an integrated circuit. Although only one conductive pad la is shown in FIG. 1, plural conductive pads 1a are formed on the surface of the semiconductor chip 1, and electric signals are supplied to and from the integrated circuit through the conductive pads 1a.
The features and advantages of the semiconductor integrated circuit device will be more clearly understood from the following description taken in conjunction with the accompanying drawings in which:
FIG. 1 is a cross sectional view showing the structure of the prior art ball grid array semiconductor integrated circuit device;
FIG. 2 is a cross sectional view showing the structure of another prior art ball grid array semiconductor integrated circuit device;
Structure of Semiconductor Integrated Circuit Device
FIGS. 5 and 6 illustrate a semiconductor integrated circuit device embodying the present invention. In FIG. 5, the semiconductor integrated circuit device is partially cut away so as to clearly understand the inside under a ball grid array.
The semiconductor integrated circuit device largely comprises a semiconductor chip 21, an interconnection 22 and a protective structure 23. Plural circuit components such as, for example, input transistors 21a are fabricated on a semiconductor substrate, and form in combination an integrated circuit. The semiconductor substrate, a multi-layered conductive pattern, a multi-layered inter-level insulating structure and a passivation layer as a whole constitute the semiconductor chip 21. The integrated circuit is connected to conductive pads 21c/21d, and the conductive pads 21c/21d are patterned on peripheral areas of a surface on both sides of the semiconductor chip 21.