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US 5,962,893 AGranted
Schottky tunneling device
AssigneeKabushiki Kaisha Toshiba
InventorsIchiro Omura, Takashi Shinohe
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AssigneeKabushiki Kaisha Toshiba
InventorsIchiro Omura, Takashi Shinohe
Estimating the term…
An n-semiconductor layer is arranged on a low-resistance n-substrate. A drain electrode is in ohmic contact with the n-substrate. A source electrode forms a Schottky junction with the n-semiconductor layer. A gate electrode is arranged adjacent to the source electrode on the n-semiconductor layer through a gate insulating film. When a voltage is applied to the gate electrode to lower the Schottky barrier height at the interface between the source electrode and the n-semiconductor layer, electrons are injected from the source electrode into the n-semiconductor layer, and a current flows in the semiconductor device. A diffusion layer which prevents a decrease in manufacturing time is not required to form in the n-semiconductor layer, and a channel which causes an increase in ON state voltage is not present.
A semiconductor device comprising:
Dependencies are inferred from the claim text.
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No related US applications are recorded in the indexed filing history.
VDMOS having built-in components: the built-in components being Schottky barrier diodes
Manufacture or treatment: of igbts
Insulated-gate bipolar transistors [IGBT]: vertical IGBTs
Having non-planar surfaces, e.g. having trenches, recesses or pillars in the surfaces of the emitter, base or collector regions: having gate…
Term ended 16 Jan 2016 (estimated)
USPTO file history isn’t available for this patent, so only indexed dates are shown.
1. Field of the Invention
The present invention relates to a semiconductor device which operates similarly to a semiconductor device having a MOS gate structure such as a MOSFET or an IGBT, and a method of manufacturing the same.
2. Description of the Related Art
The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate presently preferred embodiments of the invention, and together with the general description given above and the detailed description of the preferred embodiments given below, serve to explain the principles of the invention.
FIG. 1 is a cross sectional view showing a semiconductor device according to an embodiment of the present invention;
FIG. 2 is a graph showing the potential distribution of the semiconductor device taken along the line II--II in FIG. 1;
Preferred embodiments of the present invention will be described below with reference to the accompanying drawings.
FIG. 1 is a cross sectional view showing a semiconductor device according to an embodiment of the present invention.
In FIG. 1, reference numeral 1 denotes a low-resistance n-semiconductor substrate consisting of silicon. A silicon n-semiconductor layer 2 is formed on the n-substrate 1 by epitaxial growth. A source electrode 4 (first main electrode) in the shape of strip, island or annulus forms a Schottky junction with the surface of the n-semiconductor layer 2. Examples of the material of the source electrode 4 are Al, Au, Pt, Ti, and Pd.