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AssigneesSharp Laboratories of America, Inc., Sharp Kabushiki Kaisha
InventorsSheng Teng Hsu, Jong Jan Lee
Estimating the term…
A method of forming a semiconductor structure having a ferroelectric memory (FEM) gate unit on a silicon substrate includes implanting doping impurities of a first type into the substrate to form a conductive channel of a first type, implanting doping impurities of a second type in the conductive channel of the first type to form a conductive channel well of a second type, implanting doping impurities of a third type in the conductive channel well of the second type to form a conductive channel of a third type for use as a gate junction region, implanting doping impurities of a fourth type in the conductive channel sub-well of the third type on either side of the gate junction region to form plural conductive channels of a fourth type for use as a source junction region and a drain junction region; and depositing an FEM gate unit over the gate junction region. A ferroelectric memory cell includes a silicon substrate of a first conductive type, a well structure of a second conductive type formed in the substrate, a structure of a third conductive type formed in the well structure, for use as a gate junction region. A source junction region and a drain junction region are located in the sub-well on either side of the gate junction region, doped to form conductive channels of a fourth type. A FEM gate unit overlays the conductive channel of the third type. An insulating layer overlays the junction regions, the FEM gate unit and the substrate. Suitable electrodes are connected to the various active regions in the memory cell.
A ferroelectric memory (FEM) cell comprising:
Dependencies are inferred from the claim text.
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Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless…
Using electric elements: using ferroelectric elements
Ferroelectric ram [feram] devices comprising ferroelectric memory transistors
Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors: characterised by the memory core region
Term ended 7 Mar 2017 (estimated)
USPTO file history isn’t available for this patent, so only indexed dates are shown.
This application relates to ferroelectric thin films which are used in nonvolatile memories and specifically to a shallow junction metal-ferroelectric-metal-silicon semi-conductor. Known ferroelectric random access memories (FRAM) are constructed with one transistor (1T) and one capacitor (1C). The capacitor is generally made by sandwiching a thin ferroelectric film between two conductive electrodes, which electrodes are usually made of platinum. The circuit configuration and the read/write sequence of this type of memory are similar to that of conventional dynamic random access memories (DRAM), except that no data refreshing is necessary in a FRAM. Known FRAMs have a fatigue problem that has been observed in the ferroelectric capacitor, which is one of the major obstacles that limit the viable commercial use of such memories. The fatigue is the result of a decrease in the switchable polarization (stored nonvolatile charge) that occurs with an increased number of switching cycles. As used in this case, "switching cycles" refers to the sum of reading and writing pulses in the memory.
Another known use of ferroelectric thin films in memory applications is to form a ferroelectric-gate-controlled field effect transistor (FET) by depositing the ferroelectric thin film directly onto the gate area of the FET. Such ferroelectric-gate controlled devices have been known for some time and include devices known as metal-ferroelectric-silicon (MFS) FETs. FRAMs incorporating the MFS FET structure have two major advantages over the transistor-capacitor configuration: (1) The MFS FET occupies less surface area, and (2) provides a non-destructive readout (NDR). The latter feature enables a MFS FET device to be read thousands of times without switching the ferroelectric polarization. Fatigue, therefore, is not a significant concern when using MFS FET devices. Various forms of MFS FET structures may be constructed, such as metal ferroelectric insulators silicon (MFIS) FET, metal ferroelectric metal silicon (MFMS) FET, and metal ferroelectric metal oxide silicon (MFMOS) FET.
There are a number of problems that must be overcome in order to fabricate an efficient MFS FET device. The first problem is that it is difficult to form an acceptable crystalline ferroelectric thin film directly on silicon. Such structure is shown in U.S. Pat. No. 3,832,700. Additionally, it is very difficult to have a clean interface between the ferroelectric material and the silicon. Further, there is a problem retaining an adequate charge in the ferroelectric material. A FEM structure on a gate region is shown in U.S. Pat. No. 5,303,182, which emphasizes that the transfer of metal ions into the gate region is undesirable. Similar structure is shown in U.S. Pat. No. 5,416,735.
FIG. 1 depicts a FEM cell constructed according to the invention.
FIG. 2(a)-(b) is a graph of I.sub.D vs. V.sub.G for the FEM gate unit of the invention.
FIG. 3(a)-(c) depicts the P-E hysteresis loops for a variety of FEM gate units.
The ferroelectric memory (FEM) cell of the invention may be formed on a SOI (SIMOX) substrate, or, it may be formed in a bulk silicon substrate. The description herein will concentrate on the formation of the FEM gate unit on a bulk silicon substrate.
Turning now to FIG. 1, a silicon substrate is depicted at 10. Substrate 10, in the preferred embodiment is a single-crystal substrate, and is formed of bulk silicon. Other embodiments may be formed on a SOI substrate. As used herein, "silicon substrate" refers to either a bulk silicon substrate or a SOI substrate, or to any other suitable silicon-based substrate. As depicted in FIG. 1, the p.sup.- substrate 10 has doping impurities of a first type, which is a boron or boron compound, of a concentration of about 1.0.multidot.10.sup.15 cm.sup.-3 to 5.0.multidot.10.sup.15 cm.sup.-3
A shallow n.sup.- type layer 12, also referred to herein as conductive channel of a second type, which has doping impurities of a second type, is then formed under the gate area by phosphorous or arsenic implantation. The ion energy is in the range of 10 keV to 50 keV and the dose is in the range of 1.0.multidot.10.sup.12 cm.sup.-2 to 1.0.multidot.10.sup.13 cm.sup.-2.