Method for controlling linewidth by etching bottom anti-reflective coating

A method for forming a patterned layer within an integrated circuit comprising:

• providing a substrate;
• forming upon the substrate a blanket target layer;
• forming upon the blanket target layer a blanket conformal dielectric layer;
• forming upon the blanket conformal dielectric layer a blanket focusing layer, the blanket focusing layer being formed from an organic polymer anti-reflective coating (ARC) material, the blanket focusing layer being susceptible to a reproducible negative etch bias within a first etch method employed in forming from the blanket focusing layer a patterned focusing layer, the first etch method being a first plasma etch method employing a reactant gas composition comprising carbon tetrafluoride and argon without oxygen;
• forming upon the blanket focusing layer a blanket photoresist layer;
• photoexposing and developing the blanket photoresist layer to form a patterned photoresist layer;
• pre-treating and stabilizing through a plasma pre-treatment method the patterned photoresist layer to form a pre-treated patterned photoresist layer, the plasma pre-treatment method employing a plasma pre-treatment gas composition comprising carbon tetrafluoride and argon without oxygen;
• etching through the first etch method the blanket focusing layer to form the patterned focusing layer while employing the pre-treated patterned photoresist layer as a first etch mask layer, the patterned focusing layer having the reproducible negative etch bias with respect to the patterned photoresist layer;
• etching through a second etch method the blanket conformal dielectric layer to form a patterned conformal dielectric layer while employing the patterned focusing layer as a second etch mask layer, the patterned conformal dielectric having a reproducible second etch bias with respect to the patterned focusing layer;
• and
• etching through a third etch method the blanket target layer to form a patterned target layer while employing the patterned conformal dielectric layer as a third etch mask layer, the patterned target layer having a reproducible third etch bias with respect to the patterned conformal dielectric layer.

A method for forming a gate electrode within an integrated circuit comprising:

• providing a substrate;
• forming upon the substrate a blanket gate electrode material layer;
• forming upon the blanket gate electrode material layer a blanket focusing layer, the blanket focusing layer being formed from an organic polymer anti-reflective coating (ARC) material, the blanket focusing layer being susceptible to a reproducible negative etch bias within a first etch method employed in forming from the blanket focusing layer a patterned focusing layer, the first etch method being a first plasma etch method employing a reactant gas composition comprising carbon tetrafluoride and argon without oxygen;
• forming upon the blanket focusing layer a blanket photoresist layer;
• photoexposing and developing the blanket photoresist layer to form a patterned photoresist layer;
• pre-treating and stabilizing through a plasma pre-treatment method the patterned photoresist layer to form a pre-treated patterned photoresist layer, the plasma pre-treatment method employing a plasma pre-treatment gas composition comprising carbon tetrafluoride and argon without oxygen;
• etching through the first etch method the blanket focusing layer to form the patterned focusing layer while employing the pre-treated patterned photoresist layer as a first etch mask layer, the patterned focusing layer having the reproducible negative etch bias with respect to the patterned photoresist layer;
• and
• etching through a second etch method the blanket gate electrode material layer to form a gate electrode while employing the patterned focusing layer as a second etch mask layer, the gate electrode having a reproducible second etch bias with respect to the patterned focusing layer.

A method for forming a gate electrode layer within an integrated circuit comprising:

• providing a substrate;
• forming upon the substrate a blanket gate electrode material layer;
• forming upon the blanket gate electrode material layer a blanket conformal dielectric layer;
• forming upon the blanket conformal dielectric layer a blanket focusing layer, the blanket focusing layer being formed from an organic polymer anti-reflective coating (ARC) material, the blanket focusing layer being susceptible to a reproducible negative etch bias within a first etch method employed in forming from the blanket focusing layer a patterned focusing layer, the first etch method being a first plasma etch method employing a reactant gas composition comprising carbon tetrafluoride and argon without oxygen;
• forming upon the blanket focusing layer a blanket photoresist layer;
• photoexposing and developing the blanket photoresist layer to form a patterned photoresist layer;
• pre-treating and stabilizing through a plasma pre-treatment method the patterned photoresist layer to form a pre-treated patterned photoresist layer, the plasma pre-treatment method employing a plasma pre-treatment gas composition comprising carbon tetrafluoride and argon without oxygen;
• etching through the first etch method the blanket focusing layer to form the patterned focusing layer while employing the pre-treated patterned photoresist layer as a first etch mask layer, the patterned focusing layer having the reproducible negative etch bias with respect to the patterned photoresist layer;
• etching through a second etch method the blanket conformal dielectric layer to form a patterned conformal dielectric layer while employing the patterned focusing layer as a second etch mask layer, the patterned conformal dielectric having a reproducible second etch bias with respect to the patterned focusing layer;
• and
• etching through a third etch method the blanket gate electrode material layer to form a gate electrode while employing the patterned conformal dielectric layer as a third etch mask layer, the gate electrode having a reproducible third etch bias with respect to the patterned conformal dielectric layer.