Parallel test circuit for semiconductor memory device

A parallel test circuit for high-speed memory cell testing a semiconductor memory device having a memory array with multiple memory cells and multiple comparing means, the test circuit comprising:

• multiple first comparing means performing a first comparison of data transmitted through multiple data output lines, the data output lines being formed near memory blocks of said memory array;
• second comparing means coupled to said multiple first comparing means for performing a second comparison of data output from said first comparing means;
• multiplexing means for providing data output from said second comparing means to a multiplexing means output terminal;
• first switching means having a first input terminal and a first output terminal;
• second switching means having a second input terminal and a second output terminal, the first and second input terminals being connected to the multiplexing means output terminal;
• and
• a data output buffer having a third input terminal, the first and second output terminals of the first and second switching means, respectively being alternately connected to the third input terminal, the data output buffer for buffering the output of said multiplexing means;
• said multiplexing means being connected to said first switching means during a first mode and to said second switching means during a second mode.