Processor based BIST for an embedded memory

The processor based Built-in Self-Test (BIST) Macro for testing a memory embedded in logic, comprising:

• a clock circuit providing timing signals;
• an instruction storage storing test instructions for testing at least one memory array;
• a programmable processor reading said test instructions, generating test patterns in response to read said test instructions, and sequencing said test instructions;
• an address generator generating address schedules for said test instructions;
• a data generator generating data-input to a tested one of said at least one memory array and expected data-output from said tested memory array;
• redundancy allocation logic monitoring and identifying failures within said tested memory array and allocating redundant word lines and data lines to replace identified failing said word lines and said data lines;
• a control circuit providing control signals to control testing said tested memory array responsive to said timing signals and said test instruction;
• a boundary pipe latch stage connected at each input and output of said BIST macro and providing scannable capabilities to said inputs and outputs to improve test coverage;
• and
• wherein said instructions storage comprises:
• a first Read-Only-Memory (ROM) storing said test instructions;
• and
• a second ROM controlling and altering the execution sequence of said test instructions.

A redundancy allocation logic circuit for monitoring failures within a memory embedded in logic, said memory being provided with redundant word lines and data lines said redundancy allocation logic circuit replacing monitored said failures with said word lines and said data lines, said circuit comprising:

• means for determining a presence of failures in word lines or data lines of a memory array;
• means for storing a line address of said determined failures;
• means for determining a `greater than` predetermined number of said failures occurring at one or more said line address;
• and
• means for optimizing allocation of redundant word lines and redundant data lines, thereby maximizing a probability of repairing said failures within an embedded memory.

An integrated chip comprising:

• a plurality of stackable arrays forming a DRAM, said DRAM being embedded in logic;
• a decoder decoding addresses for each of said stackable arrays;
• an instructions storage storing test instructions for testing each of said stackable arrays;
• a programmable processor reading said test instructions, generating test patterns responsive to said test instructions, and sequencing said test instructions;
• and
• redundancy allocation logic monitoring and identifying failures within said DRAM, accumulating failing memory addresses for each said tested memory array identifying elements having multiple failures addresses of said identified elements being must fix addresses and allocating redundant word lines and data lines to replace identified failing lines.

In a logic integrated circuit (IC) chip, stackable arrays forming a modular DRAM, said DRAM being embedded in said logic, said DRAM being provided with redundant word lines and redundant data lines, said DRAM comprising:

• a processor based BIST circuit for testing said DRAM;
• redundancy allocation logic for monitoring failures within said DRAM and for allocating said redundant work lines and data lines for replacing failing said lines and further comprising:
• a data comparator comparing observed data at outputs of said DRAM to expected data,
• a `greater than` enabling circuit identifying `a must fix` word line responsive to results from said data comparator,
• a word address resister storing identified failing said word line addresses said word address register comprising a word address comparator comparing a previously stored said failing word address to a current said failing word address, wherein said current failing word address is stored in said word address register if it was not previously stored therein and further allocating a redundant word line to replace said failing word line at said failing stored address;
• and
• a pre-decoder determining a configuration of said plurality of stackable arrays.

A method of testing a semiconductor structure, said semiconductor structure including an integrated circuit chip, said integrated circuit chip including a programmable processor, a memory array, an instruction storage, a comparator and a redundancy repair circuit, said method comprising:

• a) presenting a test instruction from said instruction storage to said programmable processor;
• b) providing a test pattern to a memory array responsive to said presented test instruction;
• c) comparing in said comparator results of said provided test pattern against an expected result;
• d) storing an address for each failing said result and identifying must fail addresses by:
• i) accumulating failing memory addresses, and
• ii) identifying elements of a first type having multiple failures. addresses of said identified elements being must fix addresses;
• and
• e) repeating a-d until all memory locations have been tested.