Method and apparatus for propagating a signal between synchronous clock domains operating at a non-integer frequency ratio

A controller for use in a computer system, the controller comprising:

• a first circuit operable in a first clock domain clocked by a relatively fast clock signal;
• a second circuit operable in a second clock domain clocked by a relatively slow clock signal, the fast and slow clock signals being substantially synchronous and having respective frequencies that are non-integer multiples;
• a first latch, operable in the first clock domain, coupled to latch a first state of an input signal in response to commencement of a first period of the fast clock signal which is substantially coincident with the commencement of a first period of the slow clock signal, to generate a first output signal corresponding to the latched first state of the input signal and to hold a state of the first output signal over the first and at least one further period of the fast clock signal;
• and
• a second latch, operable in the second clock domain, coupled to latch the state of the first output signal in response to the commencement of a second period of the slow clock signal, the second period immediately following the first period of the slow clock signal.

A computer system comprising:

• a first processor;
• a second processor;
• a controller coupled to the first processor via a first bus and to the second processor via a second bus, the controller including:
• a first interface coupled to the first bus, and operable in a first clock domain clocked by a relatively fast clock signal;
• a second interface coupled to the second bus, and operable in a second clock domain clocked by a relatively slow clock signal, the first and second clock signals being substantially synchronous and having respective frequencies that are non-integer multiples;
• a first latch, operable in the first clock domain, coupled to latch a first state of an input signal, received from the first interface, in response to commencement of a first period of the fast clock signal which is substantially coincident with the commencement of a first period of the slow clock signal, to generate a first output signal corresponding to the latched first state of the input signal and to hold a state of the first output signal over the first and at least one further period of the fast clock signal;
• and
• a second latch, operable in the second clock domain, coupled to latch the state of the first output signal in response to the commencement of a second period of the slow clock signal, the second period immediately following the first period of the slow clock signal, to generate a second output signal corresponding to the latched state of the first output signal, and to propagate the second output signal to the second interface.

A computer system comprising:

• a first processor coupled to a first bus operable in a first clock domain clocked by a relatively fast clock signal;
• a second processor coupled to a second bus operable in a second clock domain clocked by a relatively slow clock signal;
• a first latch, operable in the first clock domain, coupled to latch a first state of an input signal in response to commencement of a first period of the fast clock signal which is substantially coincident with the commencement of a first period of the slow clock signal, to generate a first output signal corresponding to the latched first state of the input signal and to hold a state of the first output signal over the first and at least one further period of the fast clock signal;
• and
• a second latch, operable in the second clock domain, coupled to latch the state of the first output signal in response to the commencement of a second period of the slow clock signal, the second period immediately following the first period of the slow clock signal, to generate a second output signal corresponding to the latched state of the first output signal, and to propagate the second output signal to the second processor.