Data processor and data processing system
AssigneeHitachi, Ltd.
InventorsHironobu Hasegawa, Hiroyuki Sasaki, Masahiko Uraguchi
Life of this patent
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Abstract
A data processor has a ROM that holds a boot program for causing the CPU to transfer a debug program from a serial interface circuit to a debug-use RAM area. When supplied externally with an SDI boot command, the serial interface circuit outputs an SDI interrupt request signal (SDI.sub.-- boot) to an interrupt controller. The signal causes the CPU to execute the boot program. Debug operations are varied as per the contents of the downloaded debug program, and data exchanges upon debugging are carried out serially.
Claims21
In a data processor formed on a semiconductor chip, said data processor comprising:
- an internal bus, a central processing unit coupled to said internal bus, a storage unit coupled to said internal bus and accessible by said central processing unit, an interrupt controller coupled to said internal bus and for controlling interrupts to said central processing unit, and a serial interface unit coupled to said internal bus and for outputting and inputting data serially to and from the outside of said data processor;
- wherein said storage unit includes a rewritable first storage area;
- and
- wherein said central processing unit transfers a debug control program from said serial interface unit to said first storage area responding with said serial interface unit receiving and decoding a first command, and executes a predetermined instruction of said debug control program in said first storage area responding with said serial interface unit receiving and decoding a second command.
In a data processor formed on a semiconductor chip, said data processor comprising:
- a central processing unit, a storage unit accessible by said central processing unit, an interrupt controller for controlling interrupts to said central processing unit, and a serial interface unit;
- wherein said serial interface unit includes a flag operable both externally and by said central processing unit, a data register accessible both externally and by said central processing unit, and a command decoder for receiving and decoding an externally supplied command, said serial interface unit further permitting asynchronous serial data input and output between said data processor and the outside thereof;
- wherein said storage unit includes a rewritable first storage area for transferring a debug control program from said serial interface unit by said central processing unit;
- and
- wherein, in response to a first command included in said externally supplied command said central processing unit gains access to said data register if said flag is in a first state, said central processing unit further changing said flag to a second state when access to said data register is completed.
Dependencies are inferred from the claim text.