US 5,961,639 AGranted

Processor and method for dynamically inserting auxiliary instructions within an instruction stream during execution

AssigneeInternational Business Machines Corporation

InventorsSoummya Mallick, Robert G. McDonald, Edward L. Swarthout

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Abstract

A processor and method of executing a program within a processor are provided. According to the method, a plurality of program instructions comprising a program and a set of auxiliary instructions are stored. An instruction stream including selected ones of the plurality of program instructions is supplied to the processor. In response to the processor processing a program instruction within the instruction stream that has an associated auxiliary instruction within the set of auxiliary instructions, the associated auxiliary instruction is automatically inserted within the instruction stream and the associated auxiliary instruction is executed within the processor.

Claims16

Dependent claims

A method of executing a program within a processor, said method comprising:

supplying, to said processor, a program including a plurality of threads and a plurality of thread descriptors that are each associated with a respective one of said plurality of threads, wherein each thread includes a plurality of program instructions;
identifying, in one or more of said plurality of thread descriptors, a respective set of auxiliary instructions to be executed as part of the associated thread;
in response to said processor processing a thread within said program for which the associated thread descriptor identifies a set of auxiliary instructions:
automatically inserting at least one auxiliary instruction from said set of auxiliary instructions into the processor's instruction stream at a position in the instruction stream indicated by the associated thread descriptor;
and
executing said at least one auxiliary instruction within said processor.

3 more elements

A processor, comprising:

a first portion of memory, wherein said first portion of memory stores a program comprising a plurality of threads and a plurality of thread descriptors that are each associated with a respective one of said plurality of threads, wherein each thread includes a plurality of program instructions;
a second portion of memory, wherein said second portion of memory stores at least one set of auxiliary instructions, wherein each of said at least one set of auxiliary instructions is identified in the thread descriptor of one of said plurality of threads;
an execution core;
means for supplying one or more threads to said execution core for processing;
and
means, responsive to said execution core processing a thread within said program for which the associated thread descriptor identifies a set of auxiliary instructions, for automatically inserting at least one auxiliary instruction from said set of auxiliary instructions into the execution core's instruction stream at a position in the instruction stream indicated by the associated thread descriptor such that said at least one auxiliary instruction is subsequently executed within said execution core.

3 more elements

Dependencies are inferred from the claim text.

Facts

Application: 08/767,492Filed 16 Dec 1996
Granted: 5 Oct 1999
Term ends: Not estimatedThe source records don’t support an estimate.

Classification16 codes

G06F 9/4881
By program, e.g. task dispatcher, supervisor, operating system: scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues
G06F 9/30087
To perform miscellaneous control operations, e.g. NOP: synchronisation or serialisation instructions
G06F 9/3009
To perform miscellaneous control operations, e.g. NOP: thread control instructions
G06F 9/30185
Instruction operation extension or modification: according to one or more bits in the instruction, e.g. prefix, sub-opcode