US 5,961,638 AGranted

Branch prediction mechanism employing branch selectors to select a branch prediction

AssigneeAdvanced Micro Devices, Inc.

InventorThang M. Tran

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Abstract

A branch prediction apparatus is provided which stores multiple branch selectors corresponding to instruction bytes within a cache line of instructions or portion thereof. The branch selectors identify a branch prediction to be selected if the corresponding instruction byte is the byte indicated by the offset of the fetch address used to fetch the cache line. Instead of comparing pointers to the branch instructions with the offset of the fetch address, the branch prediction is selected simply by decoding the offset of the fetch address and choosing the corresponding branch selector. The branch prediction apparatus may operate at a higher frequencies (i.e. lower clock cycles) than if the pointers to the branch instruction and the fetch address were compared (a greater than or less than comparison). The branch selectors directly determine which branch prediction is appropriate according to the instructions being fetched, thereby decreasing the amount of logic employed to select the branch prediction.

Claims22

Dependent claims

A microprocessor comprising:

an instruction cache configured to store a plurality of instructions included within a plurality of contiguous instruction bytes, wherein said plurality of instructions includes at least one branch instruction, and wherein said instruction cache is configured to output said plurality of contiguous instruction bytes responsive to a fetch address identifying one of said plurality of instructions;
and
a branch prediction unit coupled to said instruction cache, wherein said branch prediction unit comprises:
a storage circuit configured to store branch prediction information corresponding to said plurality of contiguous instruction bytes and a plurality of branch selectors corresponding to said plurality of instructions, wherein each branch selector is information identifying a branch prediction;
a first circuit configured to select one of said plurality of branch selectors corresponding to said one of said plurality of instructions responsive to a control signal from a second circuit, said second circuit configured to generate the control signal responsive to said fetch address,
a third circuit configured to select one branch prediction corresponding to the at least one branch instruction responsive to the one of the plurality of branch selectors selected by the first circuit.

3 more elements

A microprocessor comprising:

an instruction cache configured to store lines of instructions including a first line of instructions having a first instruction, wherein said instruction cache is configured to output said first line of instructions responsive to a fetch address identifying said first instruction;
and
a branch prediction unit coupled to said instruction cache, wherein said branch prediction unit comprises;
a storage circuit configured to store branch prediction information corresponding to said first line of instructions and a plurality of branch selectors corresponding to said first line of instructions;
a branch selector circuit coupled to the storage circuit and configured to select at least one of the plurality of branch selectors as a function of the fetch address identifying the first instruction;
a branch prediction selection circuit configured to select one branch prediction corresponding to the at least one branch instruction responsive to the one of the plurality of branch selectors selected by the first circuit.

3 more elements

A method for performing branch prediction, the method comprising:

allocating a first branch selector to each byte within a first group of contiguous bytes of a line of contiguous instruction bytes, wherein a last byte of the first group of contiguous instructions defines a last byte of a first predicted taken branch instruction, and wherein the first branch selector identifies a first branch prediction corresponding to said first predicted taken branch instruction;
allocating a second branch selector to each byte within a second group of contiguous bytes of the line of contiguous instruction bytes, wherein a last byte of the second group of contiguous instruction bytes defines a last byte of the line of instruction bytes, and wherein the second branch selector identifies a sequential prediction;
fetching said line of contiguous instruction bytes from an instruction cache responsive to a fetch address;
selecting one of said first and second branch selectors responsive to said fetch address;
and
generating a subsequent fetch address responsive to selecting one of said first and second branch selectors.

3 more elements

Dependencies are inferred from the claim text.