Checkpoint table for selective instruction flushing in a speculative execution unit

A method for restoring a state of a floating point register rename table, the method comprising the steps of:

• dispatching floating point instructions to a floating point unit ("FPU");
• storing, in a floating point register rename table associated with the FPU a state of the FPU for each of the dispatched floating point instructions, wherein each of the state includes identification of registers utilized by the each of the dispatched floating point instructions;
• and
• storing, in a checkpoint table, a state of the floating point register rename table for one or more of the dispatched floating point instructions, wherein the dispatched floating point instructions are non-store instructions, have not been previously committed, and each have a new GID.

A method for restoring a state of a floating point register rename table, the method comprising the steps of:

• dispatching floating point instructions to a floating point unit ("FPU");
• storing, in a floating point register rename table associated with the FPU a state of the FPU for each of the dispatched floating point instructions, wherein each of the state includes identification of registers utilized by the each of the dispatched floating point instructions;
• and
• storing, in a checkpoint table, a state of the floating point register rename table for one or more of the dispatched floating point instructions, wherein each the state of the floating point register rename table identifies architected register(s), physical register(s), and a valid bit, if asserted, identifying a newest association of a physical register to a particular logical register, wherein each entry of the checkpoint table includes (1) a valid bit vector containing the valid bit for each the state of the floating point register rename table, and (2) a tag indicating a group of instructions bounded by outstanding branch or interruptible instructions.

A data processing system comprising:

• a processor;
• mass storage;
• main memory;
• and
• a bus system coupling the processor to the mass storage and to the main memory, wherein the processor further includes:
• an instruction dispatch unit operable for dispatching instructions to various execution units, including a floating point unit ("FPU");
• a floating point register rename table associated with the FPU and operable for storing states of registers of the FPU for dispatched floating point instructions;
• a checkpoint table operable for storing states of the floating point register rename table for one or more of the dispatched floating point instructions, wherein each of the states of the floating point register rename table identifies architected register(s), physical register(s), and a valid bit, wherein each entry of the checkpoint table includes a valid bit vector containing the valid bit for each of the states of the floating point register rename table, wherein the each entry of the checkpoint table includes a program order tag;
• and
• circuitry for restoring, when a branch instruction is determined to be mispredicted, the floating point register rename table to a state before the mispredicted branch instruction by replacing the valid bit vector of the floating point register rename table with the valid bit vector of an entry of the checkpoint table whose program order tag is oldest of all program order tags in the checkpoint table that are newer or as old as the program order tag of the mispredicted branch instruction, wherein the dispatched floating point instructions are non-store instructions, and have not been previously committed, wherein each entry of the checkpoint table includes (1) a valid bit vector containing the valid bit for each the state of the floating point register rename table, (2) a program order tag, and (3) a location pointer indicating a first available empty entry in the rename table at a time when the checkpoint entry is entered, (4) a tag indicating a group of instructions which are bounded by outstanding branch or interruptible instructions and which includes an instruction that causes the checkpoint table entry to be created.