Three input arithmetic logic unit with barrel rotator and mask generator

A data processing apparatus comprising:

• an arithmetic logic unit having first, second and third data inputs for multibit digital signals representing corresponding first, second and third input signals, and a function control input for receiving a function signal, said arithmetic logic unit generating at an output a multibit digital signal representing a mixed arithmetic and Boolean combination of said first, second and third inputs corresponding to said function signal, said mixed arithmetic and Boolean combination including at least an arithmetic combination of only said first and second inputs and an arithmetic combination of only said first and third inputs;
• a first data source supplying a first multibit digital signal to said first data input of said arithmetic logic unit;
• a second data source supplying a second multibit digital signal;
• a barrel rotator having a data input connected to said second data source, a rotate control input receiving a rotate control signal, and a data output connected to said second data input of the arithmetic logic unit, said barrel rotator left rotating said second multibit digital signal an amount corresponding to said rotate control signal and supplying said left rotated second multibit digital signal to said second data input of said arithmetic logic unit;
• a third data source supplying a third multibit digital signal;
• a mask generator having a data input connected to said third data source and a data output connected to said third data input of said arithmetic logic unit, said mask generator generating a multibit digital mask signal corresponding to said third multibit digital signal;
• and
• a plurality of data registers including
• a first output connected to said first data input of said arithmetic logic unit for recalling from a first specified data register data stored therein, thereby forming said first data source,
• a second output connected to said data input of said barrel rotator for recalling form a second specified data register data stored therein, thereby forming said second data source,
• a third output connected to said data input of said mask generator for recalling from a third specified data register data stored therein, thereby forming said third source,
• a first input connected to said output of said arithmetic logic unit for storing in a fourth specified one of said data registers said combination of said first, second and third input signals, and
• a predetermined one of said plurality of data registers being a special function data register storing therein a default mask amount;
• and
• said input of said mask generator receives said default mask amount of said special function data register.

A data processing apparatus comprising:

• an arithmetic logic unit having first, second and third data inputs for multibit digital signals representing corresponding first, second and third input signals, and a function control input for receiving a function signal, said arithmetic logic unit generating at an output a multibit digital signal representing a mixed arithmetic and Boolean combination of said first, second and third inputs corresponding to said function signal, said mixed arithmetic and Boolean combination including at least an arithmetic combination of only said first and second inputs and an arithmetic combination of only said first and third inputs;
• a first data source supplying a first multibit digital signal to said first data input of said arithmetic logic unit;
• a second data source supplying a second multibit digital signal;
• a barrel rotator having a data input connected to said second data source, a rotate control input receiving a rotate control signal, and a data output connected to said second data input of the arithmetic logic unit, said barrel rotator left rotating said second multibit digital signal an amount corresponding to said rotate control signal and supplying said left rotated second multibit digital signal to said second data input of said arithmetic logic unit;
• a third data source supplying a third multibit digital signal;
• and
• a mask generator having a data input connected to said third data source and a data output connected to said third data input of said arithmetic logic unit, said mask generator generating a multibit digital mask signal corresponding to said third multibit digital signal, said mask generator supplying to said third data input of said arithmetic logic unit said multibit digital mask signal having a number of right justified "1's" corresponding to said third multibit digital signal.

A data processing apparatus comprising:

• an arithmetic logic unit having first, second and third data inputs for multibit digital signals representing corresponding first, second and third input signals, and a function control input for receiving a function signal, said arithmetic logic unit generating at an output a multibit digital signal representing a mixed arithmetic and Boolean combination of said first, second and third inputs corresponding to said function signal, said mixed arithmetic and Boolean combination including at least an arithmetic combination of only said first and second inputs and an arithmetic combination of only said first and third inputs;
• a first data source supplying a first multibit digital signal to said first data input of said arithmetic logic unit;
• a second data source supplying a second multibit digital signal;
• a barrel rotator having a data input connected to said second data source, a rotate control input receiving a rotate control signal, and a data output connected to said second data input of the arithmetic logic unit, said barrel rotator left rotating said second multibit digital signal an amount corresponding to said rotate control signal and supplying said left rotated second multibit digital signal to said second data input of said arithmetic logic unit;
• a third data source supplying a third multibit digital signal;
• and
• a mask generator having a data input connected to said third data source and a data output connected to said third data input of said arithmetic logic unit, said mask generator generating a multibit digital mask signal corresponding to said third multibit digital signal, said mask generator supplying to said third data input of said arithmetic logic unit said multibit digital mask signal having a number of right justified "0's" corresponding to said third multibit digital signal.

A data processing apparatus comprising:

• an arithmetic logic unit having first, second and third data inputs for multibit digital signals representing corresponding first, second and third input signals, and a function control input for receiving a function signal, said arithmetic logic unit generating at an output a multibit digital signal representing a mixed arithmetic and Boolean combination of said first, second and third inputs corresponding to said function signal, said mixed arithmetic and Boolean combination including at least an arithmetic combination of only said first and second inputs and an arithmetic combination of only said first and third inputs;
• a first data source supplying a first multibit digital signal to said first data input of said arithmetic logic unit;
• a second data source supplying a second multibit digital signal;
• a barrel rotator having a data input connected to said second data source, a rotate control input receiving a rotate control signal, and a data output connected to said second data input of the arithmetic logic unit, said barrel rotator left rotating said second multibit digital signal an amount corresponding to said rotate control signal and supplying said left rotated second multibit digital signal to said second data input of said arithmetic logic unit;
• a third data source supplying a third multibit digital signal;
• and
• a mask generator having a data input connected to said third data source and a data output connected to said third data input of said arithmetic logic unit, said mask generator generating a multibit digital mask signal corresponding to said third multibit digital signal, said mask generator supplying to said third data input of said arithmetic logic unit said multibit digital mask signal having a number of left justified "1's" corresponding to said third multibit digital signal.

A data processing apparatus comprising:

• an arithmetic logic unit having first, second and third data inputs for multibit digital signals representing corresponding first, second and third input signals, and a function control input for receiving a function signal, said arithmetic logic unit generating at an output a multibit digital signal representing a mixed arithmetic and Boolean combination of said first, second and third inputs corresponding to said function signal, said mixed arithmetic and Boolean combination including at least an arithmetic combination of only said first and second inputs and an arithmetic combination of only said first and third inputs;
• a first data source supplying a first multibit digital signal to said first data input of said arithmetic logic unit;
• a second data source supplying a second multibit digital signal;
• a barrel rotator having a data input connected to said second data source, a rotate control input receiving a rotate control signal, and a data output connected to said second data input of the arithmetic logic unit, said barrel rotator left rotating said second multibit digital signal an amount corresponding to said rotate control signal and supplying said left rotated second multibit digital signal to said second data input of said arithmetic logic unit;
• a third data source supplying a third multibit digital signal;
• and
• a mask generator having a data input connected to said third data source and a data output connected to said third data input of said arithmetic logic unit, said mask generator generating a multibit digital mask signal corresponding to said third multibit digital signal, said mask generator supplying to said third data input of said arithmetic logic unit said multibit digital mask signal having a number of left justified "0's" corresponding to said third multibit digital signal.

A data processing apparatus comprising:

• an arithmetic logic unit having first, second and third data inputs for multibit digital signals representing corresponding first, second and third input signals, and a function control input for receiving a function signal, said arithmetic logic unit generating at an output a multibit digital signal representing a mixed arithmetic and Boolean combination of said first, second and third inputs corresponding to said function signal, said mixed arithmetic and Boolean combination including at least an arithmetic combination of only said first and second inputs and an arithmetic combination of only said first and third inputs;
• a first data source supplying a first multibit digital signal to said first data input of said arithmetic logic unit;
• a second data source supplying a second multibit digital signal;
• a barrel rotator having a data input connected to said second data source, a rotate control input receiving a rotate control signal, and a data output connected to said second data input of the arithmetic logic unit, said barrel rotator left rotating said second multibit digital signal an amount corresponding to said rotate control signal and supplying said left rotated second multibit digital signal to said second data input of said arithmetic logic unit;
• a third data source supplying a third multibit digital signal;
• and
• a mask generator having a data input connected to said third data source and a data output connected to said third data input of said arithmetic logic unit, said mask generator generating a multibit digital mask signal corresponding to said third multibit digital signal, said mask generator supplying to said third data input of said arithmetic logic unit said multibit digital mask signal corresponding to a bit specific unary operation on said second multibit digital signal, said bit specific unary operation of said mask generator generating a number corresponding to the bit position of a left most "1" in said third multibit digital signal.

A data processing apparatus comprising:

• an arithmetic logic unit having first, second and third data inputs for multibit digital signals representing corresponding first, second and third input signals, and a function control input for receiving a function signal, said arithmetic logic unit generating at an output a multibit digital signal representing a mixed arithmetic and Boolean combination of said first, second and third inputs corresponding to said function signal, said mixed arithmetic and Boolean combination including at least an arithmetic combination of only said first and second inputs and an arithmetic combination of only said first and third inputs;
• a first data source supplying a first multibit digital signal to said first data input of said arithmetic logic unit;
• a second data source supplying a second multibit digital signal;
• a barrel rotator having a data input connected to said second data source, a rotate control input receiving a rotate control signal, and a data output connected to said second data input of the arithmetic logic unit, said barrel rotator left rotating said second multibit digital signal an amount corresponding to said rotate control signal and supplying said left rotated second multibit digital signal to said second data input of said arithmetic logic unit;
• a third data source supplying a third multibit digital signal;
• and
• a mask generator having a data input connected to said third data source and a data output connected to said third data input of said arithmetic logic unit, said mask generator generating a multibit digital mask signal corresponding to said third multibit digital signal, said mask generator supplying to said third data input of said arithmetic logic unit said multibit digital mask signal corresponding to a bit specific unary operation on said second multibit digital signal, said bit specific unary operation of said mask generator generating a number corresponding to the bit position of a right most "1" in said third multibit digital signal.

A data processing apparatus comprising:

• an arithmetic logic unit having first, second and third data inputs for multibit digital signals representing corresponding first, second and third input signals, and a function control input for receiving a function signal, said arithmetic logic unit generating at an output a multibit digital signal representing a mixed arithmetic and Boolean combination of said first, second and third inputs corresponding to said function signal, said mixed arithmetic and Boolean combination including at least an arithmetic combination of only said first and second inputs and an arithmetic combination of only said first and third inputs;
• a first data source supplying a first multibit digital signal to said first data input of said arithmetic logic unit;
• a second data source supplying a second multibit digital signal;
• a barrel rotator having a data input connected to said second data source, a rotate control input receiving a rotate control signal, and a data output connected to said second data input of the arithmetic logic unit, said barrel rotator left rotating said second multibit digital signal an amount corresponding to said rotate control signal and supplying said left rotated second multibit digital signal to said second data input of said arithmetic logic unit;
• a third data source supplying a third multibit digital signal;
• and
• a mask generator having a data input connected to said third data source and a data output connected to said third data input of said arithmetic logic unit, said mask generator generating a multibit digital mask signal corresponding to said third multibit digital signal, said mask generator supplying to said third data input of said arithmetic logic unit said multibit digital mask signal corresponding to a bit specific unary operation on said second multibit digital signal, said bit specific unary operation of said mask generator generates a number corresponding to the bit position of a left most bit in said third multibit digital signal which differs from a most significant bit of said third multibit digital signal.

A data processing apparatus comprising:

• an arithmetic logic unit having first, second and third data inputs for multibit digital signals representing corresponding first, second and third input signals, and a function control input for receiving a function signal, said arithmetic logic unit generating at an output a multibit digital signal representing a mixed arithmetic and Boolean combination of said first, second and third inputs corresponding to said function signal, said mixed arithmetic and Boolean combination including at least an arithmetic combination of only said first and second inputs and an arithmetic combination of only said first and third inputs;
• a first data source supplying a first multibit digital signal to said first data input of said arithmetic logic unit;
• a second data source supplying a second multibit digital signal;
• a barrel rotator having a data input connected to said second data source, a rotate control input receiving a rotate control signal, and a data output connected to said second data input of the arithmetic logic unit, said barrel rotator left rotating said second multibit digital signal an amount corresponding to said rotate control signal and supplying said left rotated second multibit digital signal to said second data input of said arithmetic logic unit;
• a third data source supplying a third multibit digital signal;
• and
• a mask generator having a data input connected to said third data source and a data output connected to said third data input of said arithmetic logic unit, said mask generator generating a multibit digital mask signal corresponding to said third multibit digital signal, said mask generator supplying to said third data input of said arithmetic logic unit said multibit digital mask signal corresponding to a bit specific unary operation on said second multibit digital signal, said bit specific unary operation of said mask generator generating a number corresponding to the bit position of a right most bit in said third multibit digital signal which differs from a least significant bit of said third multibit digital number.

A data processing apparatus comprising:

• an arithmetic logic unit having first, second and third data inputs for multibit digital signals representing corresponding first, second and third input signals, and a function control input for receiving a function signal, said arithmetic logic unit generating at an output a multibit digital signal representing a mixed arithmetic and Boolean combination of said first, second and third inputs corresponding to said function signal, said mixed arithmetic and Boolean combination including at least an arithmetic combination of only said first and second inputs and an arithmetic combination of only said first and third inputs;
• a first data source supplying a first multibit digital signal to said first data input of said arithmetic logic unit;
• a second data source supplying a second multibit digital signal;
• a barrel rotator having a data input connected to said second data source, a rotate control input receiving a rotate control signal, and a data output connected to said second data input of the arithmetic logic unit, said barrel rotator left rotating said second multibit digital signal an amount corresponding to said rotate control signal and supplying said left rotated second multibit digital signal to said second data input of said arithmetic logic unit;
• a third data source supplying a third multibit digital signal;
• and
• a mask generator having a data input connected to said third data source and a data output connected to said third data input of said arithmetic logic unit, said mask generator generating a multibit digital mask signal corresponding to said third multibit digital signal, said mask generator supplying to said third data input of said arithmetic logic unit said multibit digital mask signal corresponding to a bit specific unary operation on said second multibit digital signal, said bit specific unary operation of said mask generator generating a number corresponding to a selected one of either the bit position of a left most "1" in said third multibit digital signal, the bit position of a right most "1" in said third multibit digital signal, the bit position of a left most bit in said third multibit digital signal which differs from a most significant bit of said third multibit digital signal, or the bit position of a right most bit in said third multibit digital signal which differs from a least significant bit of said third multibit digital number.

A data processing apparatus comprising:

• an arithmetic logic unit having first, second and third data inputs for multibit digital signals representing corresponding first, second and third input signals, and a function control input for receiving a function signal, said arithmetic logic unit generating at an output a multibit digital signal representing a mixed arithmetic and Boolean combination of said first, second and third inputs corresponding to said function signal, said mixed arithmetic and Boolean combination including at least an arithmetic combination of only said first and second inputs and an arithmetic combination of only said first and third inputs;
• a first data source supplying a first multibit digital signal to said first data input of said arithmetic logic unit;
• a second data source supplying a second multibit digital signal;
• a barrel rotator having a data input connected to said second data source, a rotate control input receiving a rotate control signal, and a data output connected to said second data input of the arithmetic logic unit, said barrel rotator left rotating said second multibit digital signal an amount corresponding to said rotate control signal and supplying said left rotated second multibit digital signal to said second data input of said arithmetic logic unit;
• a third data source supplying a third multibit digital signal;
• and
• a mask generator having a data input connected to said third data source and a data output connected to said third data input of said arithmetic logic unit, said mask generator generating a multibit digital mask signal corresponding to said third multibit digital signal, said mask generator forming said multibit digital mask as a digital pattern repeated an integral number of times.

A data processing apparatus comprising:

• an arithmetic logic unit having first, second and third data inputs for multibit digital signals representing corresponding first, second and third input signals, and a function control input for receiving a function signal, said arithmetic logic unit generating at an output a multibit digital signal representing a mixed arithmetic and Boolean combination of said first, second and third inputs corresponding to said function signal, said mixed arithmetic and Boolean combination including at least an arithmetic combination of only said first and second inputs and an arithmetic combination of only said first and third inputs;
• a first data source supplying a first multibit digital signal to said first data input of said arithmetic logic unit;
• a second data source supplying a second multibit digital signal;
• a barrel rotator having a data input connected to said second data source, a rotate control input receiving a rotate control signal, and a data output connected to said second data input of the arithmetic logic unit, said barrel rotator left rotating said second multibit digital signal an amount corresponding to said rotate control signal and supplying said left rotated second multibit digital signal to said second data input of said arithmetic logic unit;
• a third data source supplying a third multibit digital signal;
• and
• a mask generator having a data input connected to said third data source and a data output connected to said third data input of said arithmetic logic unit, said mask generator generating a multibit digital mask signal corresponding to said third multibit digital signal, said mask generator supplies to said third data input of said arithmetic logic unit a number corresponding to the replication of a selected number of bits of said third multibit digital signal a selected number of times.

A data processing apparatus comprising:

• an arithmetic logic unit having first, second and third data inputs for multibit digital signals representing corresponding first, second and third input signals, and a function control input for receiving a function signal, said arithmetic logic unit generating at an output a multibit digital signal representing a mixed arithmetic and Boolean combination of said first, second and third inputs corresponding to said function signal, said mixed arithmetic and Boolean combination including at least an arithmetic combination of only said first and second inputs and an arithmetic combination of only said first and third inputs;
• a first data source supplying a first multibit digital signal to said first data input of said arithmetic logic unit;
• a second data source supplying a second multibit digital signal;
• a barrel rotator having a data input connected to said second data source, a rotate control input receiving a rotate control signal, and a data output connected to said second data input of the arithmetic logic unit, said barrel rotator left rotating said second multibit digital signal an amount corresponding to said rotate control signal and supplying said left rotated second multibit digital signal to said second data input of said arithmetic logic unit;
• a third data source supplying a third multibit digital signal;
• a mask generator having a data input connected to said third data source and a data output connected to said third data input of said arithmetic logic unit, said mask generator generating a multibit digital mask signal corresponding to said third multibit digital signal;
• at least one additional mask generator, each additional mask generator generating a corresponding additional multibit digital mask signal;
• and
• a third input multiplexer having a first input connected to said mask generator and at least one additional input mask generator input, each additional mask generator input connected to a corresponding additional mask generator for supplying a selected one of either said first multibit digital mask or a corresponding additional multibit digital mask to said third data input of said arithmetic logic unit.

A data processing apparatus comprising:

• an arithmetic logic unit having first, second and third data inputs for multibit digital signals representing corresponding first, second and third input signals, and a function control input for receiving a function signal, said arithmetic logic unit generating at an output a multibit digital signal representing a mixed arithmetic and Boolean combination of said first, second and third inputs corresponding to said function signal, said mixed arithmetic and Boolean combination including at least an arithmetic combination of only said first and second inputs and an arithmetic combination of only said first and third inputs;
• a first data source supplying a first multibit digital signal to said first data input of said arithmetic logic unit;
• a second data source supplying a second multibit digital signal;
• a barrel rotator having a data input connected to said second data source, a rotate control input receiving a rotate control signal, and a data output connected to said second data input of the arithmetic logic unit, said barrel rotator left rotating said second multibit digital signal an amount corresponding to said rotate control signal and supplying said left rotated second multibit digital signal to said second data input of said arithmetic logic unit;
• a third data source supplying a third multibit digital signal;
• a mask generator having a data input connected to said third data source and a data output connected to said third data input of said arithmetic logic unit, said mask generator generating a multibit digital mask signal corresponding to said third multibit digital signal;
• a special function data register storing therein a default barrel rotate amount;
• said rotate control input of said barrel rotator receives said default barrel rotate amount of said special function data register;
• and
• said input of said mask generator receives said default barrel rotate amount of said special function data register.

A data processing apparatus comprising:

• an arithmetic logic unit having first, second and third data inputs for multibit digital signals representing corresponding first, second and third input signals, and a function control input for receiving a function signal, said arithmetic logic unit generating at an output a multibit digital signal representing a mixed arithmetic and Boolean combination of said first, second and third inputs corresponding to said function signal, said mixed arithmetic and Boolean combination including at least an arithmetic combination of only said first and second inputs and an arithmetic combination of only said first and third inputs;
• a first data source supplying a first multibit digital signal to said first data input of said arithmetic logic unit;
• a second data source supplying a second multibit digital signal;
• a barrel rotator having a data input connected to said second data source, a rotate control input receiving a rotate control signal, and a data output connected to said second data input of the arithmetic logic unit, said barrel rotator left rotating said second multibit digital signal an amount corresponding to said rotate control signal and supplying said left rotated second multibit digital signal to said second data input of said arithmetic logic unit;
• a third data source supplying a third multibit digital signal;
• a mask generator having a data input connected to said third data source and a data output connected to said third data input of said arithmetic logic unit, said mask generator generating a multibit digital mask signal corresponding to said third multibit digital signal;
• a function signal generator connected to said three input arithmetic logic unit and said second data source, said function signal generator generating a first function signal if a most significant bit of said second multibit digital signal has a first state and a second function signal different from said first function signal if said most significant bit of said second multibit digital signal has a second state.

A data processing system comprising:

• a data system bus transferring data and addresses;
• an system memory connected to said data system bus, said system memory storing data and transferring system data via said data system bus;
• a data processor circuit connected to said data system bus, said data processor circuit including
• an arithmetic logic unit having first, second and third data inputs for multibit digital signals representing corresponding first, second and third input signals, and a function control input for receiving a function signal, said arithmetic logic unit generating at an output a multibit digital signal representing a mixed arithmetic and Boolean combination of said first, second and third inputs corresponding to said function signal, said mixed arithmetic and Boolean combination including at least an arithmetic combination of only said first and second inputs and an arithmetic combination of only said first and third inputs,
• a first data source supplying a first multibit digital signal to said first data input of said arithmetic logic unit,
• a second data source supplying a second multibit digital signal,
• a barrel rotator having a data input connected to said second data source, a rotate control input receiving a rotate control signal, and a data output connected to said second data input of the arithmetic logic unit, said barrel rotator left rotating said second multibit digital signal an amount corresponding to said rotate control signal and supplying said left rotated second multibit digital signal to said second data input of said arithmetic logic unit,
• a third data source supplying a third multibit digital signal, and
• a mask generator having a data input connected to said third data source and a data output connected to said third data input of said arithmetic logic unit, said mask generator generating a multibit digital mask signal corresponding to said third multibit digital signal;
• a plurality of data registers including
• a first output connected to said first data input of said arithmetic logic unit for recalling from a first specified data register data stored therein, thereby forming said first data source,
• a second output connected to said data input of said barrel rotator for recalling form a second specified data register data stored therein, thereby forming said second data source,
• a third output connected to said data input of said mask generator for recalling from a third specified data register data stored therein, thereby forming said third source,
• a first input connected to said output of said arithmetic logic unit for storing in a fourth specified one of said data registers said combination of said first, second and third input signals, and
• a predetermined one of said plurality of data registers being a special function data register storing therein a default barrel rotate amount;
• and
• said rotate control input of said barrel rotator receives said default barrel rotate amount of said special function data register.

A data processing system comprising:

• a data system bus transferring data and addresses;
• an system memory connected to said data system bus, said system memory storing data and transferring system data via said data system bus;
• a data processor circuit connected to said data system bus, said data processor circuit including
• an arithmetic logic unit having first, second and third data inputs for multibit digital signals representing corresponding first, second and third input signals, and a function control input for receiving a function signal, said arithmetic logic unit generating at an output a multibit digital signal representing a mixed arithmetic and Boolean combination of said first, second and third inputs corresponding to said function signal, said mixed arithmetic and Boolean combination including at least an arithmetic combination of only said first and second inputs and an arithmetic combination of only said first and third inputs,
• a first data source supplying a first multibit digital signal to said first data input of said arithmetic logic unit,
• a second data source supplying a second multibit digital signal,
• a barrel rotator having a data input connected to said second data source, a rotate control input receiving a rotate control signal, and a data output connected to said second data input of the arithmetic logic unit, said barrel rotator left rotating said second multibit digital signal an amount corresponding to said rotate control signal and supplying said left rotated second multibit digital signal to said second data input of said arithmetic logic unit,
• a third data source supplying a third multibit digital signal, and
• a mask generator having a data input connected to said third data source and a data output connected to said third data input of said arithmetic logic unit, said mask generator generating a multibit digital mask signal corresponding to said third multibit digital signal;
• a plurality of data registers including
• a first output connected to said first data input of said arithmetic logic unit for recalling from a first specified data register data stored therein, thereby forming said first data source,
• a second output connected to said data input of said barrel rotator for recalling form a second specified data register data stored therein, thereby forming said second data source,
• a third output connected to said data input of said mask generator for recalling from a third specified data register data stored therein, thereby forming said third source,
• a first input connected to said output of said arithmetic logic unit for storing in a fourth specified one of said data registers said combination of said first, second and third input signals, and
• a predetermined one of said plurality of data registers being a special function data register storing therein a default mask amount, and
• said input of said mask generator receives said default mask amount of said special function data register.

A data processing system comprising:

• a data system bus transferring data and addresses;
• an system memory connected to said data system bus, said system memory storing data and transferring system data via said data system bus;
• a data processor circuit connected to said data system bus, said data processor circuit including
• an arithmetic logic unit having first, second and third data inputs for multibit digital signals representing corresponding first, second and third input signals, and a function control input for receiving a function signal, said arithmetic logic unit generating at an output a multibit digital signal representing a mixed arithmetic and Boolean combination of said first, second and third inputs corresponding to said function signal, said mixed arithmetic and Boolean combination including at least an arithmetic combination of only said first and second inputs and an arithmetic combination of only said first and third inputs,
• a first data source supplying a first multibit digital signal to said first data input of said arithmetic logic unit,
• a second data source supplying a second multibit digital signal,
• a barrel rotator having a data input connected to said second data source, a rotate control input receiving a rotate control signal, and a data output connected to said second data input of the arithmetic logic unit, said barrel rotator left rotating said second multibit digital signal an amount corresponding to said rotate control signal and supplying said left rotated second multibit digital signal to said second data input of said arithmetic logic unit,
• a third data source supplying a third multibit digital signal, and
• a mask generator having a data input connected to said third data source and a data output connected to said third data input of said arithmetic logic unit, said mask generator generating a multibit digital mask signal corresponding to said third multibit digital signal, said mask generator supplying to said third data input of said arithmetic logic unit said multibit digital mask signal having a number of right justified "1's" corresponding to said third multibit digital signal.

A data processing system comprising:

• a data system bus transferring data and addresses;
• an system memory connected to said data system bus, said system memory storing data and transferring system data via said data system bus;
• a data processor circuit connected to said data system bus, said data processor circuit including
• an arithmetic logic unit having first, second and third data inputs for multibit digital signals representing corresponding first, second and third input signals, and a function control input for receiving a function signal, said arithmetic logic unit generating at an output a multibit digital signal representing a mixed arithmetic and Boolean combination of said first, second and third inputs corresponding to said function signal, said mixed arithmetic and Boolean combination including at least an arithmetic combination of only said first and second inputs and an arithmetic combination of only said first and third inputs,
• a first data source supplying a first multibit digital signal to said first data input of said arithmetic logic unit,
• a second data source supplying a second multibit digital signal,
• a barrel rotator having a data input connected to said second data source, a rotate control input receiving a rotate control signal, and a data output connected to said second data input of the arithmetic logic unit, said barrel rotator left rotating said second multibit digital signal an amount corresponding to said rotate control signal and supplying said left rotated second multibit digital signal to said second data input of said arithmetic logic unit,
• a third data source supplying a third multibit digital signal, and
• a mask generator having a data input connected to said third data source and a data output connected to said third data input of said arithmetic logic unit, said mask generator generating a multibit digital mask signal corresponding to said third multibit digital signal, said mask generator supplying to said third data input of said arithmetic logic unit said multibit digital mask signal having a number of right justified "0's" corresponding to said third multibit digital signal.

A data processing system comprising:

• a data system bus transferring data and addresses;
• an system memory connected to said data system bus, said system memory storing data and transferring system data via said data system bus;
• a data processor circuit connected to said data system bus, said data processor circuit including
• an arithmetic logic unit having first, second and third data inputs for multibit digital signals representing corresponding first, second and third input signals, and a function control input for receiving a function signal, said arithmetic logic unit generating at an output a multibit digital signal representing a mixed arithmetic and Boolean combination of said first, second and third inputs corresponding to said function signal, said mixed arithmetic and Boolean combination including at least an arithmetic combination of only said first and second inputs and an arithmetic combination of only said first and third inputs,
• a first data source supplying a first multibit digital signal to said first data input of said arithmetic logic unit,
• a second data source supplying a second multibit digital signal,
• a barrel rotator having a data input connected to said second data source, a rotate control input receiving a rotate control signal, and a data output connected to said second data input of the arithmetic logic unit, said barrel rotator left rotating said second multibit digital signal an amount corresponding to said rotate control signal and supplying said left rotated second multibit digital signal to said second data input of said arithmetic logic unit,
• a third data source supplying a third multibit digital signal, and
• a mask generator having a data input connected to said third data source and a data output connected to said third data input of said arithmetic logic unit, said mask generator generating a multibit digital mask signal corresponding to said third multibit digital signal, said mask generator supplying to said third data input of said arithmetic logic unit said multibit digital mask signal having a number of left justified "1's" corresponding to said third multibit digital signal.

A data processing system comprising:

• a data system bus transferring data and addresses;
• an system memory connected to said data system bus, said system memory storing data and transferring system data via said data system bus;
• a data processor circuit connected to said data system bus, said data processor circuit including
• an arithmetic logic unit having first, second and third data inputs for multibit digital signals representing corresponding first, second and third input signals, and a function control input for receiving a function signal, said arithmetic logic unit generating at an output a multibit digital signal representing a mixed arithmetic and Boolean combination of said first, second and third inputs corresponding to said function signal, said mixed arithmetic and Boolean combination including at least an arithmetic combination of only said first and second inputs and an arithmetic combination of only said first and third inputs,
• a first data source supplying a first multibit digital signal to said first data input of said arithmetic logic unit,
• a second data source supplying a second multibit digital signal,
• a barrel rotator having a data input connected to said second data source, a rotate control input receiving a rotate control signal, and a data output connected to said second data input of the arithmetic logic unit, said barrel rotator left rotating said second multibit digital signal an amount corresponding to said rotate control signal and supplying said left rotated second multibit digital signal to said second data input of said arithmetic logic unit,
• a third data source supplying a third multibit digital signal, and
• a mask generator having a data input connected to said third data source and a data output connected to said third data input of said arithmetic logic unit, said mask generator generating a multibit digital mask signal corresponding to said third multibit digital signal, said mask generator supplying to said third data input of said arithmetic logic unit said multibit digital mask signal having a number of left justified "0's" corresponding to said third multibit digital signal.

A data processing system comprising:

• a data system bus transferring data and addresses;
• an system memory connected to said data system bus, said system memory storing data and transferring system data via said data system bus;
• a data processor circuit connected to said data system bus, said data processor circuit including
• an arithmetic logic unit having first, second and third data inputs for multibit digital signals representing corresponding first, second and third input signals, and a function control input for receiving a function signal, said arithmetic logic unit generating at an output a multibit digital signal representing a mixed arithmetic and Boolean combination of said first, second and third inputs corresponding to said function signal, said mixed arithmetic and Boolean combination including at least an arithmetic combination of only said first and second inputs and an arithmetic combination of only said first and third inputs,
• a first data source supplying a first multibit digital signal to said first data input of said arithmetic logic unit,
• a second data source supplying a second multibit digital signal,
• a barrel rotator having a data input connected to said second data source, a rotate control input receiving a rotate control signal, and a data output connected to said second data input of the arithmetic logic unit, said barrel rotator left rotating said second multibit digital signal an amount corresponding to said rotate control signal and supplying said left rotated second multibit digital signal to said second data input of said arithmetic logic unit,
• a third data source supplying a third multibit digital signal, and
• a mask generator having a data input connected to said third data source and a data output connected to said third data input of said arithmetic logic unit, said mask generator generating a multibit digital mask signal corresponding to said third multibit digital signal, said mask generator supplying to said third data input of said arithmetic logic unit said multibit digital mask signal corresponding to a bit specific unary operation on said second multibit digital signal, said bit specific unary operation of mask generator generating a number corresponding to the bit position of a left most "1" in said third multibit digital signal.

A data processing system comprising:

• a data system bus transferring data and addresses;
• an system memory connected to said data system bus, said system memory storing data and transferring system data via said data system bus;
• a data processor circuit connected to said data system bus, said data processor circuit including
• an arithmetic logic unit having first, second and third data inputs for multibit digital signals representing corresponding first, second and third input signals, and a function control input for receiving a function signal, said arithmetic logic unit generating at an output a multibit digital signal representing a mixed arithmetic and Boolean combination of said first, second and third inputs corresponding to said function signal, said mixed arithmetic and Boolean combination including at least an arithmetic combination of only said first and second inputs and an arithmetic combination of only said first and third inputs,
• a first data source supplying a first multibit digital signal to said first data input of said arithmetic logic unit,
• a second data source supplying a second multibit digital signal,
• a barrel rotator having a data input connected to said second data source, a rotate control input receiving a rotate control signal, and a data output connected to said second data input of the arithmetic logic unit, said barrel rotator left rotating said second multibit digital signal an amount corresponding to said rotate control signal and supplying said left rotated second multibit digital signal to said second data input of said arithmetic logic unit,
• a third data source supplying a third multibit digital signal, and
• a mask generator having a data input connected to said third data source and a data output connected to said third data input of said arithmetic logic unit, said mask generator generating a multibit digital mask signal corresponding to said third multibit digital signal, said mask generator supplying to said third data input of said arithmetic logic unit said multibit digital mask signal corresponding to a bit specific unary operation on said second multibit digital signal, said bit specific unary operation of said mask generator generating a number corresponding to the bit position of a right most "1" in said third multibit digital signal.

A data processing system comprising:

• a data system bus transferring data and addresses;
• an system memory connected to said data system bus, said system memory storing data and transferring system data via said data system bus;
• a data processor circuit connected to said data system bus, said data processor circuit including
• an arithmetic logic unit having first, second and third data inputs for multibit digital signals representing corresponding first, second and third input signals, and a function control input for receiving a function signal, said arithmetic logic unit generating at an output a multibit digital signal representing a mixed arithmetic and Boolean combination of said first, second and third inputs corresponding to said function signal, said mixed arithmetic and Boolean combination including at least an arithmetic combination of only said first and second inputs and an arithmetic combination of only said first and third inputs,
• a first data source supplying a first multibit digital signal to said first data input of said arithmetic logic unit,
• a second data source supplying a second multibit digital signal,
• a barrel rotator having a data input connected to said second data source, a rotate control input receiving a rotate control signal, and a data output connected to said second data input of the arithmetic logic unit, said barrel rotator left rotating said second multibit digital signal an amount corresponding to said rotate control signal and supplying said left rotated second multibit digital signal to said second data input of said arithmetic logic unit,
• a third data source supplying a third multibit digital signal, and
• a mask generator having a data input connected to said third data source and a data output connected to said third data input of said arithmetic logic unit, said mask generator generating a multibit digital mask signal corresponding to said third multibit digital signal, said mask generator supplying to said third data input of said arithmetic logic unit said multibit digital mask signal corresponding to a bit specific unary operation on said second multibit digital signal, said bit specific unary operation of said mask generator generating a number corresponding to the bit position of a left most bit in said third multibit digital signal which differs from a most significant bit of said third multibit digital signal.

A data processing system comprising:

• a data system bus transferring data and addresses;
• an system memory connected to said data system bus, said system memory storing data and transferring system data via said data system bus;
• a data processor circuit connected to said data system bus, said data processor circuit including
• an arithmetic logic unit having first, second and third data inputs for multibit digital signals representing corresponding first, second and third input signals, and a function control input for receiving a function signal, said arithmetic logic unit generating at an output a multibit digital signal representing a mixed arithmetic and Boolean combination of said first, second and third inputs corresponding to said function signal, said mixed arithmetic and Boolean combination including at least an arithmetic combination of only said first and second inputs and an arithmetic combination of only said first and third inputs,
• a first data source supplying a first multibit digital signal to said first data input of said arithmetic logic unit,
• a second data source supplying a second multibit digital signal,
• a barrel rotator having a data input connected to said second data source, a rotate control input receiving a rotate control signal, and a data output connected to said second data input of the arithmetic logic unit, said barrel rotator left rotating said second multibit digital signal an amount corresponding to said rotate control signal and supplying said left rotated second multibit digital signal to said second data input of said arithmetic logic unit,
• a third data source supplying a third multibit digital signal, and
• a mask generator having a data input connected to said third data source and a data output connected to said third data input of said arithmetic logic unit, said mask generator generating a multibit digital mask signal corresponding to said third multibit digital signal, said mask generator supplying to said third data input of said arithmetic logic unit said multibit digital mask signal corresponding to a bit specific unary operation on said second multibit digital signal, said bit specific unary operation of said mask generator generating a number corresponding to the bit position of a right most bit in said third multibit digital signal which differs from a least significant bit of said third multibit digital number.

A data processing system comprising:

• a data system bus transferring data and addresses;
• an system memory connected to said data system bus, said system memory storing data and transferring system data via said data system bus;
• a data processor circuit connected to said data system bus, said data processor circuit including
• an arithmetic logic unit having first, second and third data inputs for multibit digital signals representing corresponding first, second and third input signals, and a function control input for receiving a function signal, said arithmetic logic unit generating at an output a multibit digital signal representing a mixed arithmetic and Boolean combination of said first, second and third inputs corresponding to said function signal, said mixed arithmetic and Boolean combination including at least an arithmetic combination of only said first and second inputs and an arithmetic combination of only said first and third inputs,
• a first data source supplying a first multibit digital signal to said first data input of said arithmetic logic unit,
• a second data source supplying a second multibit digital signal,
• a barrel rotator having a data input connected to said second data source, a rotate control input receiving a rotate control signal, and a data output connected to said second data input of the arithmetic logic unit, said barrel rotator left rotating said second multibit digital signal an amount corresponding to said rotate control signal and supplying said left rotated second multibit digital signal to said second data input of said arithmetic logic unit,
• a third data source supplying a third multibit digital signal, and
• a mask generator having a data input connected to said third data source and a data output connected to said third data input of said arithmetic logic unit, said mask generator generating a multibit digital mask signal corresponding to said third multibit digital signal, said mask generator supplying to said third data input of said arithmetic logic unit said multibit digital mask signal corresponding to a bit specific unary operation on said second multibit digital signal, said bit specific unary operation of said mask generator generating a number corresponding to a selected one of either the bit position of a left most "1" in said third multibit digital signal, the bit position of a right most "1" in said third multibit digital signal, the bit position of a left most bit in said third multibit digital signal which differs from a most significant bit of said third multibit digital signal, or the bit position of a right most bit in said third multibit digital signal which differs from a least significant bit of said third multibit digital number.

A data processing system comprising:

• a data system bus transferring data and addresses;
• an system memory connected to said data system bus, said system memory storing data and transferring system data via said data system bus;
• a data processor circuit connected to said data system bus, said data processor circuit including
• an arithmetic logic unit having first, second and third data inputs for multibit digital signals representing corresponding first, second and third input signals, and a function control input for receiving a function signal, said arithmetic logic unit generating at an output a multibit digital signal representing a mixed arithmetic and Boolean combination of said first, second and third inputs corresponding to said function signal, said mixed arithmetic and Boolean combination including at least an arithmetic combination of only said first and second inputs and an arithmetic combination of only said first and third inputs,
• a first data source supplying a first multibit digital signal to said first data input of said arithmetic logic unit,
• a second data source supplying a second multibit digital signal,
• a barrel rotator having a data input connected to said second data source, a rotate control input receiving a rotate control signal, and a data output connected to said second data input of the arithmetic logic unit, said barrel rotator left rotating said second multibit digital signal an amount corresponding to said rotate control signal and supplying said left rotated second multibit digital signal to said second data input of said arithmetic logic unit,
• a third data source supplying a third multibit digital signal, and
• a mask generator having a data input connected to said third data source and a data output connected to said third data input of said arithmetic logic unit, said mask generator generating a multibit digital mask signal corresponding to said third multibit digital signal, said mask generator forming said multibit digital mask as a digital pattern repeated an integral number of times.

A data processing system comprising:

• a data system bus transferring data and addresses;
• an system memory connected to said data system bus, said system memory storing data and transferring system data via said data system bus;
• a data processor circuit connected to said data system bus, said data processor circuit including
• an arithmetic logic unit having first, second and third data inputs for multibit digital signals representing corresponding first, second and third input signals, and a function control input for receiving a function signal, said arithmetic logic unit generating at an output a multibit digital signal representing a mixed arithmetic and Boolean combination of said first, second and third inputs corresponding to said function signal, said mixed arithmetic and Boolean combination including at least an arithmetic combination of only said first and second inputs and an arithmetic combination of only said first and third inputs,
• a first data source supplying a first multibit digital signal to said first data input of said arithmetic logic unit,
• a second data source supplying a second multibit digital signal,
• a barrel rotator having a data input connected to said second data source, a rotate control input receiving a rotate control signal, and a data output connected to said second data input of the arithmetic logic unit, said barrel rotator left rotating said second multibit digital signal an amount corresponding to said rotate control signal and supplying said left rotated second multibit digital signal to said second data input of said arithmetic logic unit,
• a third data source supplying a third multibit digital signal, and
• a mask generator having a data input connected to said third data source and a data output connected to said third data input of said arithmetic logic unit, said mask generator generating a multibit digital mask signal corresponding to said third multibit digital signal, said mask generator supplying to said third data input of said arithmetic logic unit a number corresponding to the replication of a selected number of bits of said third multibit digital signal a selected number of times.

A data processing system comprising:

• a data system bus transferring data and addresses;
• an system memory connected to said data system bus, said system memory storing data and transferring system data via said data system bus;
• a data processor circuit connected to said data system bus, said data processor circuit including
• an arithmetic logic unit having first, second and third data inputs for multibit digital signals representing corresponding first, second and third input signals, and a function control input for receiving a function signal, said arithmetic logic unit generating at an output a multibit digital signal representing a mixed arithmetic and Boolean combination of said first, second and third inputs corresponding to said function signal, said mixed arithmetic and Boolean combination including at least an arithmetic combination of only said first and second inputs and an arithmetic combination of only said first and third inputs,
• a first data source supplying a first multibit digital signal to said first data input of said arithmetic logic unit,
• a second data source supplying a second multibit digital signal,
• a barrel rotator having a data input connected to said second data source, a rotate control input receiving a rotate control signal, and a data output connected to said second data input of the arithmetic logic unit, said barrel rotator left rotating said second multibit digital signal an amount corresponding to said rotate control signal and supplying said left rotated second multibit digital signal to said second data input of said arithmetic logic unit,
• a third data source supplying a third multibit digital signal,
• a mask generator having a data input connected to said third data source and a data output connected to said third data input of said arithmetic logic unit, said mask generator generating a multibit digital mask signal corresponding to said third multibit digital signal,
• at least one additional mask generator, each additional mask generator generating a corresponding additional multibit digital mask signal, and
• a third input multiplexer having a first input connected to said mask generator and at least one additional mask generator input, each additional mask generator input connected to a corresponding additional mask generator for supplying a selected one of either said first multibit digital mask or a corresponding additional multibit digital mask to said third data input of said arithmetic logic unit.

A data processing system comprising:

• a data system bus transferring data and addresses;
• an system memory connected to said data system bus, said system memory storing data and transferring system data via said data system bus;
• a data processor circuit connected to said data system bus, said data processor circuit including
• an arithmetic logic unit having first, second and third data inputs for multibit digital signals representing corresponding first, second and third input signals, and a function control input for receiving a function signal, said arithmetic logic unit generating at an output a multibit digital signal representing a mixed arithmetic and Boolean combination of said first, second and third inputs corresponding to said function signal, said mixed arithmetic and Boolean combination including at least an arithmetic combination of only said first and second inputs and an arithmetic combination of only said first and third inputs,
• a first data source supplying a first multibit digital signal to said first data input of said arithmetic logic unit,
• a second data source supplying a second multibit digital signal,
• a barrel rotator having a data input connected to said second data source, a rotate control input receiving a rotate control signal, and a data output connected to said second data input of the arithmetic logic unit, said barrel rotator left rotating said second multibit digital signal an amount corresponding to said rotate control signal and supplying said left rotated second multibit digital signal to said second data input of said arithmetic logic unit,
• a third data source supplying a third multibit digital signal,
• a mask generator having a data input connected to said third data source and a data output connected to said third data input of said arithmetic logic unit, said mask generator generating a multibit digital mask signal corresponding to said third multibit digital signal,
• a special function data register storing therein a default barrel rotate amount,
• said rotate control input of said barrel rotator receives said default barrel rotate amount of said special function data register, and
• said input of said mask generator receives said default barrel rotate amount of said special function data register.

A data processing system comprising:

• a data system bus transferring data and addresses;
• an system memory connected to said data system bus, said system memory storing data and transferring system data via said data system bus;
• a data processor circuit connected to said data system bus, said data processor circuit including
• an arithmetic logic unit having first, second and third data inputs for multibit digital signals representing corresponding first, second and third input signals, and a function control input for receiving a function signal, said arithmetic logic unit generating at an output a multibit digital signal representing a mixed arithmetic and Boolean combination of said first, second and third inputs corresponding to said function signal, said mixed arithmetic and Boolean combination including at least an arithmetic combination of only said first and second inputs and an arithmetic combination of only said first and third inputs,
• a first data source supplying a first multibit digital signal to said first data input of said arithmetic logic unit,
• a second data source supplying a second multibit digital signal,
• a barrel rotator having a data input connected to said second data source, a rotate control input receiving a rotate control signal, and a data output connected to said second data input of the arithmetic logic unit, said barrel rotator left rotating said second multibit digital signal an amount corresponding to said rotate control signal and supplying said left rotated second multibit digital signal to said second data input of said arithmetic logic unit,
• a third data source supplying a third multibit digital signal,
• a mask generator having a data input connected to said third data source and a data output connected to said third data input of said arithmetic logic unit, said mask generator generating a multibit digital mask signal corresponding to said third multibit digital signal, and
• a function signal generator connected to said three input arithmetic logic unit and said second data source, said function signal generator generating a first function signal if a most significant bit of said second multibit digital signal has a first state and a second function signal different from said first function signal if said most significant bit of said second multibit digital signal has a second state.