Execution of data processing instructions

Data processing apparatus which executes successive data processing instructions in a pipelined manner, and the instructions are processed in synchronization with a clock cycle, said apparatus comprising:

• an execution unit for executing instructions to cause changes to data stored in registers and memory locations of said processor, said instructions including a first instruction and a second instruction;
• a memory management unit for accessing said memory locations in response to certain of said instructions and for generating an abort signal to indicate that a memory access by said first instruction is invalid, wherein said abort control signal is generated in a last half of the clock cycle of a first instruction;
• a condition tester for comparing condition codes in said second instruction with a plurality of flags indicating a processing state of said apparatus and generating a condition failure control signal if said codes do not match at least a first of said flags;
• and
• conditional control logic, responsive to said abort signal and to said condition failure control signal, for preventing said execution unit from changing, in response to said second instruction, data stored in registers and memory locations of said processor.

Data processing apparatus which executes successive data processing instructions in a pipelined manner, and the instructions are processed in synchronization with a clock cycle, said apparatus comprising:

• a memory management unit which accesses a data memory in response to one or more of said instructions, said memory management unit comprising detection logic to detect whether each memory access is invalid, said memory management unit generating an abort control signal to indicate that a memory access is invalid, wherein said abort control signal is generated in a last half of the clock cycle of a first instruction;
• a condition tester which responds to a processing state of said apparatus generated by previously executed instructions and which operates during execution of each instruction to detect whether that instruction should be executed, said condition tester generating a condition failure control signal to indicate that the current instruction should not be executed;
• combining logic for combining said abort control signal and said condition failure control signal to generate a combined control signal;
• and
• conditional control logic which responds to said combined control signal to stop execution of a second currently executing instruction if either said memory management unit detects that a memory access initiated by a preceding instruction is invalid or if said condition tester detects that said second currently executing instruction should not be executed.

Data processing apparatus which executes successive data processing instructions in a pipelined manner, and the instructions are processed in synchronization with a clock cycle, said apparatus comprising:

• a memory management unit which accesses a data memory in response to one or more of said instructions, said memory management unit comprising detection logic to detect whether each memory access is invalid, said memory management unit generating an abort control signal to indicate that a memory access by a previous instruction is invalid, wherein said abort control signal is generated in a last half of the clock cycle of a first instruction;
• a condition tester which operates during execution of each instruction to detect whether that instruction should be executed, said condition tester generating a condition failure control signal to indicate that the current instruction should not be executed;
• combining logic for combining said abort control signal and said condition failure control signal to generate a combined control signal having two states, wherein a first state is generated in response to receiving an abort control signal or a condition failure control signal, and a second state is generated otherwise;
• and
• conditional control logic which responds to said combined control signal to prevent complete execution of a current instruction in response to receiving a combined control signal having the first state and allowing execution of the current instruction in response to receiving a combined control signal having the second state.