Microprocessor with circuits, systems, and methods for selecting alternative pipeline instruction paths based on instruction leading codes

A method of operating a processor to process a plurality of instructions, the method comprising the steps of:

• receiving an instruction from the plurality of instructions;
• determining whether the received instruction is preceded by an instruction path leading code;
• passing the received instruction along at least one instruction path in a plurality of instruction paths;
• in response to determining that the received instruction is preceded by an instruction path leading code, selecting the single instruction decode path for the received instruction preceded by the instruction path leading code from among the plurality of instruction decode paths corresponds to the instruction path leading code;
• said step of passing the received instruction along the single instruction decode path consisting of
• passing each received instruction along a current single instruction decode path unless the received instruction is preceded by a switch and store instruction path leading code or a restore instruction path leading code,
• when a received instruction is preceded by a switch and store instruction path leading code
• storing the current single instruction decode path to thereby become a stored prior single instruction decode path, and
• passing the received instruction preceded by the switch and store instruction path leading code along a switched single instruction decode path corresponding to the switch and store instruction path leading code, the switched single instruction decode path thereby becoming the current single instruction decode path, and
• when a received instruction is preceded by a restore instruction path leading code, recalling the stored prior instruction decode path to thereby become the current instruction decode path and passing the received instruction preceded by the restore instruction path leading code along the recalled prior instruction decode path;
• wherein the plurality of instruction paths comprises:
• a first path comprising a first decode unit and operable to couple an instruction to an execute stage;
• a second path comprising a second decode unit different than the first decode unit in the first path, wherein the second path is operable to couple an instruction to the execute stage;
• and
• a third path comprising a bus connected to the execute stage;
• and
• passing the received instruction as decoded by the selected single instruction decode path to a common execute stage having instruction execution resources, wherein a received instruction decoded by any of the plurality of instruction decode paths is permitted to employ all instruction execution resources of the common execute stage.

A microprocessor for processing a plurality of instructions, said microprocessor comprising:

• circuitry for receiving an instruction from the plurality of instructions;
• circuitry for determining whether the received instruction is preceded by an instruction path leading code;
• a plurality of instruction decode paths, each instruction decode path for decoding a received instruction according to a predetermined instruction set architecture;
• circuitry for passing the received instruction along a selected one instruction decode path selected from among a plurality of instruction decode paths;
• and
• instruction decode path control circuitry connected to said circuitry for determining whether the received instruction is preceded by an instruction path leading code and to said circuitry for passing the received instruction along said selected instruction decode path, said instruction decode path control circuitry operable in response to determining that the received instruction is preceded by an instruction path leading code for selecting said one instruction decode path for the received instruction preceded by the instruction path leading code from among the plurality of instruction decode paths corresponding to the instruction path leading code;
• a common execute stage receiving said received instruction as decoded by said selected instruction decode path having instruction execution resources for executing said received instruction, wherein a received instruction decoded by any of the plurality of instruction decode paths is permitted to employ all instruction execution resources of the common execute stage.